Architecture
154
LWR Load Word Right (cont.) LWR
It is alright to put a load instruction that uses the same rt as the LWR instruction immediately before
LWR. The contents of general-purpose register rt are bypassed internally in the processor,
eliminating the need for a NOP between the two instructions.
No Address Error instruction is raised due to misalignment.
Operation :
T: vAddr ← ((offset15)16 || offset15..0) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr31..2 || (pAddr1..0 xor ReverseEndian2)
if BigEndianMem = 1 then
pAddr ← pAddr31..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
mem ← LoadMemory (uncached, WORD-byte, pAddr, vAddr, DATA)
GPR[rt] ← mem31..32-8*byte..0 || GPR[rt]31-8*byte..0
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
Address Error exception