Architecture
18
In this document (bit 0 is always the rightmost bit).
Byte addressing is used with the R3900 Processor Core, but there are alignment restrictions for halfword and
word access. Halfword access is aligned on an even byte boundary (0, 2, 4...) and word access on a byte
boundary divisible by 4 (0, 4, 8...) .
The address of multiple-byte data, as shown in Figure 2-5 above, begins at the most significant byte for the
big endian format and at the least significant byte for the little endian format.
There are special instructions (LWL, LWR, SWL, SWR) for accessing words not aligned on a word
boundary. They are used in pairs for addressing misaligned words, but involve an extra instruction cycle
which is wasted if used with properly aligned words. Figure 2-6 shows the byte arrangement when a
misaligned word is addressed at byte address 3 for the big and little endian formats.
31 24 23 1615 8 7 0
4 5 6
3
31 24 23 16 15 87 0
6 5 4
3
Figure 2-6. Byte addresses of a misaligned word
Higher address
Lower address
Higher address
Lower address
(a) Big endian
(b)Little endian