Lwr | Toshiba TX39 guide

Architecture

LWR

Load Word Right

LWR

	31	26 25		21 20		16 15		0
	LWR			base		rt		offset
				base		rt		offset
	100110
	6			5		5		16

Format :

LWR rt, offset(base)

Description :

Used together with LWL to load four consecutive bytes to a register when the bytes cross a word boundary. LWR loads the right part of the register from the appropriate part of the low-order word; LWL loads the left part of the register from the appropriate part of the high-order word.

This instruction generates a 32-bit effective address that can point to any byte, by sign-extending the 16-bit offset and adding it to the contents of general-purpose register base. Only bytes from the word in memory containing the designated starting byte are read. Depending on the starting byte, from one to four bytes are loaded.

The concept is illustrated below. This instruction (LWR) first loads the designated memory byte into the low-order (right-most) byte of the register; it then continues loading bytes from memory into the register, proceeding toward the high-order byte of the memory word and the high-order byte of the register, until it reaches the high-order byte of the memory word. The most-significant (left- most) byte of the register is not changed.

Address 4

Address 0

Memory (big endian)

4	5	6	7
0	1	2	3

	Before		Register
		A	B	C	D	$24
	loading

LWR $24,4($0)

After
loading A B C	4	$24

153

Image 164

Toshiba TX39 user manual Lwr

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 227 Bus request and bus grant 227 Cache snoop 228229 230 Architecture Architecture High-performance Risc techniques FeaturesIntroduction Low power consumption Signal notation Notation Used in This ManualMathematical notation Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Instruction Set Overview Operation code 6 bitsSource register 5 bits Destination register 5 bits Load/store ComputationalJump/branch Coprocessor ALU 3-operand, register type Computational InstructionsALU Immediate Multiply/Divide Jump/Branch InstructionsCoprocessor Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview User mode Kernel modeMemory Management Unit MMU 1 R3900 Processor Core operating modes Direct segment mapping KusegKseg0 Kseg1 Address mapping Architecture Instruction Notation Instruction Set OverviewInstruction Formats Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Instruction Format and Description Jump/Branch InstructionsJump instructions Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions BCzT, BCzF Instruction Format and Description Coprocessor InstructionsCOPz Instruction Format and Description Architecture Restore From System Control Coprocessor CP0 Instructions13. System control coprocessor CP0 instructions Cache Instruction Format and Description Pipeline Architecture Delayed branching Delay SlotDelayed load Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Exception Processing Registers Cause registerStatus register Cache register Read/Write Cause register register no.13Bits Mnemonic Field name Description ExcCode field Mnemonic Cause Status register register no.12 BitsField name Description Read Status register 1/2 Bits Mnemonic Field name Description Value on Read KUc/KUp/KUo Kernel/User mode current/previous/old IEc/IEp/IEo Interrupt Enable current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details Address Error exception ∙ Causes ∙ Exception mask∙ Applicable instructions ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Priority of Exceptions Exception Mnemonic Priority of ExceptionsReturn from Exception Handler Architecture Caches Instruction Cache Data cache configuration Data Cache Operation during lock Lock bit settingLock function Lock bit clearing Auto-lock bits Cache Test Function Cache disablingCache flushing Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† Debug register register no.16 DBD Debug Branch DelayDM Debug Mode 0 at reset BsF Bus Error Exception Flag SSt Single at resetNIS Non-maskable Interrupt Status OES Other Exceptions Status Debug Exceptions DSS bitTypes of debug exceptions Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Exception priorities Iii Return from a debug exception handlerExecuting a Deret instruction ∙ Exception masking Details of Debug ExceptionsSingle Step exception ∙ Cause ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Word access 32 bits Triplebyte access 24 bitsHalfword access 16 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori COPz rs OPcodeSpecial function COPz rt CP0 Function Notation TMPR3901F 200 Bus interface for ease of system implementation R3900 Processor CoreOn-chip peripheral circuits Low power consumption, optimal for portable applications Debugging support functions on chipMaximum operating frequency Package Internal Blocks R3900 Processor Core Clock generatorBus interface unit bus controller / write buffer Address protection unit 204 Instruction Iimitations ConfigurationR3900 Processor Core Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Debug Support Unit SynchronizerRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Enables internal PLL clock Mode quadruple frequency of crystal oscillatorHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze mode Operations Clock∙ Master Clock ∙ Processor Clock Clock Master clock ProcessorSystem clock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode