Architecture
158
MFCz Move From Coprocessor MFCz
31 26 25 21 20 1615 11 10 0
COPz
0100xx*
MF
00000 rt rd 0
000 0000 0000
6 5 5 5 11
Format :
MFCz rt, rd
Description :
Loads the contents of coprocessor z register rd into general-purpose register rt.
Operation :
T: GPR[rt] ← CPR[z, rd]
Exceptions :
Coprocessor Unusable exception
∗ Refer also to the table on the following page (Operation Code Bit Encoding) or to the section
entitled “Bit Encoding of CPU Instruction Opcodes” at the end of this appendix.