Toshiba TX39 user manual Cache register register no.7

Architecture

6.2.4Cache register (register no.7)

This register controls the cache lock function.

31	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0		IAL	DAL	IAL	DAL	IAL	DAL				0
		o	o	p	p	c	c
18		1	1	1	1	1	1				0

Bits	Mnemonic	Field name		Description	Value on	Read/
					Reset	Write
13	IALo	Instruction Cache	1	= cache lock enable;	0	Read/
		Lock(old)	0	= cache lock disable		Write
12	DALo	Data Cache	1	= cache lock enable;	0	Read/
		Lock(old)	0	= cache lock disable		Write
11	IALp	Instruction Cache	1	= cache lock enable;	0	Read/
		Lock(previous)	0	= cache lock disable		Write
10	DALp	Data Cache	1	= cache lock enable;	0	Read/
		Lock(previous)	0	= cache lock disable		Write
9	IALc	Instruction Cache	1	= cache lock enable;	0	Read/
		Lock(current)	0	= cache lock disable		Write
8	DALc	Data Cache	1	= cache lock enable;	0	Read/
		Lock(current)	0	= cache lock disable		Write
31-14	0		Ignored on write; 0 when read.		0	Read
7-0
		Figure 6-5. Cache register

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