Iii Return from a debug exception handler | Toshiba TX39 manual

Architecture

iii) Return from a debug exception handler

nWhen a user program exception occurs at the same time as a Debug exception, change the DEPC value so that a return will be made to the exception handler.

When NIS = 1, change DEPC to 0xBFC0 0000.

When OES = 1, change DEPC to 0x8000 0080 (if BEV = 0) or 0xBFC0 0180 (if BEV = 0).

nExecuting a DERET instruction

PC: Contains the DEPC value.

Debug register DM: Cleared to 0.

Status register KUc, IEc: Set to 1, enabling interrupts.

The forced disabling of the cache auto-lock function is cleared and becomes governed by the Cache register value.

Forced prohibition of Single Step exception is cleared, causing these to be governed by the Debug register SSt.

NmI and debug exception masks are cleared.

(3) Exception priorities

DSS has a higher priority than DBp, since it occurs in the pipeline E stage. For this reason DSS is not raised at the same time as DBp.

It is further possible for debug exceptions and user exceptions to occur simultaneously. In this case processing branches first to the debug exception handler, but the Status, Cause, EPC and BadVAddr registers are updated to the values for the user exception. DEPC is not automatically updated to the user exception vector address, so the return address must be set by user software.

It is possible for DSS to occur at the same time as an instruction fetch Address Error AdEL or instruction fetch TLB Refill exception (TLBL). DSS cannot occur simultaneously with any other exceptions except these two.

The instruction that triggers the instruction fetch Address Error AdEL or instruction fetch TLB Refill exception (TLBL) will not itself be executed, so it is not possible for DBp to occur at the same time as these two exceptions.

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Toshiba TX39 user manual Iii Return from a debug exception handler, Executing a Deret instruction, Exception priorities

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 227 Bus request and bus grant 227 Cache snoop 228229 230 Architecture Architecture Introduction FeaturesHigh-performance Risc techniques Low power consumption Signal notation Notation Used in This ManualMathematical notation Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Instruction Set Overview Operation code 6 bitsSource register 5 bits Destination register 5 bits Load/store ComputationalJump/branch Coprocessor ALU Immediate Computational InstructionsALU 3-operand, register type Multiply/Divide Jump/Branch InstructionsCoprocessor Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview User mode Kernel modeMemory Management Unit MMU 1 R3900 Processor Core operating modes Direct segment mapping KusegKseg0 Kseg1 Address mapping Architecture Instruction Formats Instruction Set OverviewInstruction Notation Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Jump instructions Jump/Branch InstructionsInstruction Format and Description Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions COPz Instruction Format and Description Coprocessor InstructionsBCzT, BCzF Instruction Format and Description Architecture Restore From System Control Coprocessor CP0 Instructions13. System control coprocessor CP0 instructions Cache Instruction Format and Description Pipeline Architecture Delayed load Delay SlotDelayed branching Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Exception Processing Registers Cause registerStatus register Cache register Bits Mnemonic Field name Description Cause register register no.13Read/Write ExcCode field Mnemonic Cause Status register register no.12 BitsField name Description Read Status register 1/2 Bits Mnemonic Field name Description Value on Read KUc/KUp/KUo Kernel/User mode current/previous/old IEc/IEp/IEo Interrupt Enable current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details Address Error exception ∙ Causes ∙ Exception mask∙ Applicable instructions ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Return from Exception Handler Priority of ExceptionsPriority of Exceptions Exception Mnemonic Architecture Caches Instruction Cache Data cache configuration Data Cache Lock function Lock bit settingOperation during lock Lock bit clearing Auto-lock bits Cache Test Function Cache disablingCache flushing Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† DM Debug Mode 0 at reset DBD Debug Branch DelayDebug register register no.16 BsF Bus Error Exception Flag SSt Single at resetNIS Non-maskable Interrupt Status OES Other Exceptions Status Debug Exceptions DSS bitTypes of debug exceptions Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Executing a Deret instruction Iii Return from a debug exception handlerException priorities Single Step exception ∙ Cause Details of Debug Exceptions∙ Exception masking ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Word access 32 bits Triplebyte access 24 bitsHalfword access 16 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori Special function OPcodeCOPz rs COPz rt CP0 Function Notation TMPR3901F 200 On-chip peripheral circuits R3900 Processor CoreBus interface for ease of system implementation Low power consumption, optimal for portable applications Debugging support functions on chipMaximum operating frequency Package Internal Blocks R3900 Processor Core Clock generatorBus interface unit bus controller / write buffer Address protection unit 204 R3900 Processor Core ConfigurationInstruction Iimitations Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Debug Support Unit SynchronizerRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Enables internal PLL clock Mode quadruple frequency of crystal oscillatorHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze mode Operations Clock∙ Master Clock ∙ Processor Clock System clock Master clock ProcessorClock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode