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Toshiba TX39 user manual Slt

Models: TX39

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Architecture

SLT

Set On Less Than

SLT

	31	26 25		21 20		16 15		11 10		6 5		0
		SPECIAL		rs		rt		rd		0		SLT
				rs		rt		rd
		000000								00000		101010
		6		5		5		5		5		6

Format :

SLT rd, rs, rt

Description :

Compares the contents of general-purpose registers rt and rs as 32-bit signed integers. A 1, if rs is less than rt, or a 0, otherwise, is placed in general-purpose register rd as the result of the comparison. No overflow exception is raised. The comparison is valid even if the subtraction used in making the comparison overflows.

Operation :

T:	if GPR[rs]< GPR[rt] then
	GPR[rd] ← 031 1
	else
	GPR[rd] ← 032
	endif

Exceptions :

None

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Image 188

Toshiba TX39 user manual Slt

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectorsAppendix a Instruction Set Details Coprocessor Unusable exceptionBus Interface Unit Bus Controller / Write Buffer 227 Bus request and bus grant 227 Cache snoop 228229 230Architecture Architecture High-performance Risc techniques FeaturesIntroduction Low power consumption Signal notation Notation Used in This ManualMathematical notation Data notationArchitecture Architecture OverviewRegisters CPU registersCP0 registers Reserved † Exception program counterInstruction Set Overview Operation code 6 bitsSource register 5 bits Destination register 5 bitsLoad/store ComputationalJump/branch CoprocessorALU 3-operand, register type Computational InstructionsALU Immediate Multiply/Divide Jump/Branch InstructionsCoprocessor Instructions Special InstructionsSpecial Instruction CP0 instructions Instruction Description CP0 InstructionsData Formats and Addressing Big endian and little endian formatsArchitecture Byte addresses of a misaligned word Pipeline Processing Overview User mode Kernel modeMemory Management Unit MMU 1 R3900 Processor Core operating modesDirect segment mapping KusegKseg0 Kseg1Address mapping Architecture Instruction Notation Instruction Set OverviewInstruction Formats Byte specifications for load and store instructions Load and Store InstructionsBase Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and DescriptionArchitecture Instruction Format and Description Jump/Branch InstructionsJump instructions Instruction in the delay slot is executed during the jump 10. Branch instructionsArchitecture Special Instructions 11. Special instructionsBCzT, BCzF Instruction Format and Description Coprocessor InstructionsCOPz Instruction Format and Description Architecture Restore From System Control Coprocessor CP0 Instructions13. System control coprocessor CP0 instructions Cache Instruction Format and DescriptionPipeline Architecture Delayed branching Delay SlotDelayed load Nonblocking Load Function Nonblocking load functionDivide Instruction DIV, Divu StreamingMemory Management Unit MMU R3900 Processor Core Operating ModesDirect Segment Mapping Internal MMU virtual address spaceKuseg 512MB Exception Processing Utlb TLBL2 Exception Processing Registers Cause registerStatus register Cache registerRead/Write Cause register register no.13Bits Mnemonic Field name Description ExcCode field Mnemonic CauseStatus register register no.12 BitsField name Description ReadStatus register 1/2 Bits Mnemonic Field name Description Value on Read KUc/KUp/KUo Kernel/User mode current/previous/old IEc/IEp/IEo Interrupt Enable current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt MaskCache register register no.7 Cache registerDALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15Config Configuration register register no.3 21-1910. Config register2/2 Exception Details Address Error exception ∙ Causes ∙ Exception mask∙ Applicable instructions ∙ ProcessingBreakpoint exception ∙ Cause ∙ ServicingBus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ CauseReset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ CauseArchitecture Priority of Exceptions Exception Mnemonic Priority of ExceptionsReturn from Exception Handler Architecture Caches Instruction CacheData cache configuration Data CacheOperation during lock Lock bit settingLock function Lock bit clearing Auto-lock bitsCache Test Function Cache disablingCache flushing ExampleCache Refill Cache refillCache Snoop Architecture Debugging Functions System Control Processor CP0 RegistersPRId Processor revision ID Debug †† Debug exception control Depc ††Debug register register no.16 DBD Debug Branch DelayDM Debug Mode 0 at reset BsF Bus Error Exception Flag SSt Single at resetNIS Non-maskable Interrupt Status OES Other Exceptions StatusDebug Exceptions DSS bitTypes of debug exceptions Debug Single Step DSSBranching to a debug exception handler Ii Debug exception handler executionException priorities Iii Return from a debug exception handlerExecuting a Deret instruction ∙ Exception masking Details of Debug ExceptionsSingle Step exception ∙ Cause ∙ Instruction causing this exception Debug Breakpoint exception ∙ CauseArchitecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operationExamples of Instruction Notation Table A-2. Common Load/Store Functions Function MeaningWord access 32 bits Triplebyte access 24 bitsHalfword access 16 bits Byte access 8 bitsJump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name DataBit# Cache Operation Description Name CFCz COPz COPzCTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCzMFCz Mfhi Mflo MTC0 MTCz MTCzMthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori COPz rs OPcodeSpecial function COPz rt CP0 FunctionNotation TMPR3901F 200 Bus interface for ease of system implementation R3900 Processor CoreOn-chip peripheral circuits Low power consumption, optimal for portable applications Debugging support functions on chipMaximum operating frequency PackageInternal Blocks R3900 Processor Core Clock generatorBus interface unit bus controller / write buffer Address protection unit204 Instruction Iimitations ConfigurationR3900 Processor Core Clock Generator Address mappingSync NOP Address Protection Unit Registers Break Address register BAddr0-1Break Mask register BMsk0-1 Break Control register BCnt0-1Break Status register BSts Memory protection exceptionDebug Support Unit SynchronizerRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1INT* signal synchronization INT50NMI* signal synchronization CPCOND* signal synchronization CPCOND31Pins Enables internal PLL clock Mode quadruple frequency of crystal oscillatorHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze modeOperations Clock∙ Master Clock ∙ Processor ClockClock Master clock ProcessorSystem clock Read Operation Single ReadBus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waitsInterrupts 1 NMI2 INT50 InterruptBus Arbitration Bus request and bus grantBUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus modePower-Down Mode Halt mode232 Standby Mode Standby mode PLL stopDoze Mode Reduced Frequency Mode