Toshiba TX39 user manual Config register2/2

Architecture

Bits		Mnemonic	Field name	Description	Value on	Read/
					Reset	Write
8		Halt††	Halt	Setting this bit to 1 puts the R3900	0	Read/
				Processor Core in Halt mode. This		Write
				state is canceled by a Reset exception
				when a reset signal is received, or
				when cancelled by a non-maskable
				interrupt signal or interrupt signal that
				clears the Halt bit to 0. The Halt bit is
				cleared even if interrupts are masked.
				Data cache snoops are not possible in
				Halt mode. Halt mode reduces power
				consumption to a greater extent than
				Doze mode.
7		Lock	Lock Config	Setting this bit to 1 prevents further	0	Reset
			register	writes to the Config register. This bit
				is cleared to 0 by a Reset exception.
				If a store instruction is used to set other
				bits at the same time as the Lock bit,
				the other settings are valid.
6		DCBR	Data Cache Burst	1:Indicates that the value in the	0	Read/
			Refill	DRSize field of the Config register		Write
				should be used as the data cache
				refill size.
				0:The data cache refill size is 1 word (4
				bytes).
5		ICE	Instruction Cache	Setting this bit to 1 enables the	1	Read/
			Enable	instruction cache.		Write
4		DCE	Data Cache	Setting this bit to 1 enables the data	1	Read/
			Enable	cache.		Write
3-2		IRSize	Instruction Burst	These bits designate the instruction	00	Read/
			Refill Size	cache burst refill size as follows.		Write
				00: 4 words (16 bytes)
				01: 8 words (32 bytes)
				10: 16 words (64 bytes)
				11: 32 words (128 bytes)
1-0		DRSize	Data Burst Refill	These bits indicate the data cache	00	Read/
			Size	burst refill size as follows. (This		Write
				setting is valid only when the DCBR bit
				in the Config register is set to 1.)
				00: 4 words (16 bytes)
				01: 8 words (32 bytes)
				10: 16 words (64 bytes)
				11: 32 words (128 bytes)
31-22,		0		Ignored on write; 0 when read	0	Read
15-12
Note :	† After modifications to DCBR, ICE, DCE, IRSize or DRSize, the new cache configuration takes effect after
	completion of the currently executing bus operation (cache refill).

††Operation is undefined when both Doze bit and Halt bit are set to 1.

Figure 6-10. Config register(2/2)

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