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TMPR3901F
218
The relationship among the clocks is shown in the table below.
Master clock
(FCLK)
RF [1:0]
Processor
clock
HALF*
System clock
(SYSCLK)
00 1
H
1
L
1/2
01
1/2
H
1/2
1
L
1/4
10
1/4
H
1/4
L
1/8
11
1/8
H
1/8
L
1/16
Contents
Main
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CONTENTS Architecture
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TMPR3901F
Page
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Chapter 1Introduction
1.1 Features
Page
1.2 Notation Used in This Manual
Page
Chapter 2 Architecture
2.1 Overview
2.2 Registers
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2.3 Instruction Set Overview
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16
2.4 Data Formats and Addressing
(b) Little endian
Figure 2-5. Big endian and little endian formats
(a) Big endian
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2.5 Pipeline Processing Overview
2.6 Memory Management Unit (MMU)
Page
Figure 2-8. Address mapping
Page
Chapter 3 Instruction Set Overview
3.1 Instruction Formats
3.2 Instruction Notation
3.3 Load and Store Instructions
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3.4 Computational Instructions
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3.5 Jump/Branch Instructions
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3.6 Special Instructions
3.7 Coprocessor Instructions
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3.8 System Control Coprocessor (CP0) Instructions
Chapter 4 Pipeline Architecture
4.1 Overview
4.2 Delay Slot
4.3 Nonblocking Load Function
4.4 Multiply and Multiply/Add Instructions(MULT, MULTU, MADD, MADDU)
4.5 Divide Instruction (DIV, DIVU)
4.6 Streaming
5.
Chapter 5 Memory Management Unit (MMU)
5.1 R3900 Processor Core Operating Modes
5.2 Direct Segment Mapping
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6.
Chapter 6 Exception Processing
6.1 Overview
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6.2 Exception Processing Registers
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Bits Mnemonic Field name Description Value on Reset Read/
Write
Figure 6-10. Config register(2/2)
6.3 Exception Details
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6.4 Priority of Exceptions
6.5 Return from Exception Handler
Page
Chapter 7 Caches
7.1 Instruction Cache
7.2 Data Cache
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7.3 Cache Test Function
7.4 Cache Refill
7.5 Cache Snoop
8.
Page
Chapter 8 Debugging Functions
8.1 System Control Processor (CP0) Registers
Page
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8.2 Debug Exceptions
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8.3 Details of Debug Exceptions
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Instruction Classes
Instruction Formats
Instruction Notation Conventions
Sign Extension and Zero Extension
Page
Examples of Instruction Notation
Load and Store Instructions
1 1 (word) 0 0
Table A-4. Load/Store byte access
Jump and Branch Instructions
ADD Add ADD
ADDI Add Immediate ADDI
ADDIU Add Immediate Unsigned ADDIU
ADDU Add Unsigned ADDU
AND And AND
ANDI And Immediate ANDI
BCzF Branch On Coprocessor z False BCzF
BCzF Branch On Coprocessor z False (cont.) BCzF
BCzFL Branch On Coprocessor z False Likely BCzFL
BCzFL Branch On Coprocessor z False Likely (cont.) BCzFL
BCzT Branch On Coprocessor z True BCzT
BCzT Branch On Coprocessor z True (cont.) BCzT
BCzTL Branch On Coprocessor z True Likely BCzTL
BCzTL Branch On Coprocessor z True Likely (cont.) BCzTL
BEQ Branch On Equal BEQ
BEQL Branch On Equal Likely BEQL
BGEZ Branch On Greater Than Or Equal To Zero BGEZ
BGEZAL Branch On Greater Than Or Equal To Zero And Link BGEZAL
BGEZALL Branch On Greater Than Or Equal To Zero And Link Likely BGEZALL
BGEZL Branch On Greater Than Or Equal To Zero Likely BGEZL
BGTZ Branch On Greater Than Zero BGTZ
BGTZL Branch On Greater Than Zero Likely BGTZL
BLEZ Branch On Less Than Or Equal To Zero BLEZ
BLEZL Branch On Less Than Or Equal To Zero Likely BLEZL
BLTZ Branch On Less Than Zero BLTZ
BLTZAL Branch On Less Than Zero And Link BLTZAL
BLTZALL Branch On Less Than Zero And Link Likely BLTZALL
BLTZL Branch On Less Than Zero Likely BLTZL
BNE Branch On Not Equal BNE
BNEL Branch On Not Equal Likely BNEL
BREAK Breakpoint BREAK
CACHE Cache CACHE
CACHE Cache (cont.) CACHE
135
CFCz Move Control From Coprocessor CFCz
CFCz 0
CFCz rt, rd
T: GPR[rt] CCR[z, rd]
* Operation Code Bit Encoding :
COPz Coprocessor Operation COPz
COPz cofun
T: CoprocessorOperation (z, cofun)
* Operation Code Bit Encoding :
COPz
CTCz Move Control To Coprocessor CTCz
DERET Debug Exception Return DERET
DIV Divide DIV
DIVU Divide Unsigned DIVU
JJump J
JAL Jump And Link JAL
JALR Jump And Link Register JALR
JR Jump Register JR
LB Load Byte LB
LB rt, offset(base)
LBU Load Byte Unsigned LBU
LH Load Halfword LH
LHU Load Halfword Unsigned LHU
LUI Load Upper Immediate LUI
LW Load Word LW
LWL Load Word Left LWL
LWL Load Word Left (cont.) LWL
LWR Load Word Right LWR
LWR Load Word Right (cont.) LWR
MADD Multiply/Add MADD
MADDU Multiply/Add Unsigned MADDU
MFC0 Move From System Control Coprocessor MFC0
MFCz Move From Coprocessor MFCz
MFCz Move From Coprocessor (cont.) MFCz
*Operation Code Bit Encoding :
MFHI Move From HI MFHI
MFLO Move From LO MFLO
MTC0 Move To System Control Coprocessor MTC0
MTCz Move To Coprocessor MTCz
MTHI Move To HI MTHI
MTLO Move To LO MTLO
MULT Multiply MULT
MULTU Multiply Unsigned MULTU
NOR Nor NOR
OR Or OR
ORI Or Immediate ORI
RFE Restore From Exception RFE
SB Store Byte SB
SDBBP Software Debug Breakpoint SDBBP
SH Store Halfword SH
SLL Shift Left Logical SLL
SLLV Shift Left Logical Variable SLLV
SLT Set On Less Than SLT
SLTI Set On Less Than Immediate SLTI
SLTIU Set On Less Than Immediate Unsigned SLTIU
SLTU Set On Less Than Unsigned SLTU
SRA Shift Right Arithmetic SRA
SRAV Shift Right Arithmetic Variable SRAV
SRL Shift Right Logical SRL
SRLV Shift Right Logical Variable SRLV
SUB Subtract SUB
SUBU Subtract Unsigned SUBU
SW Store Word SW
SWL Store Word Left SWL
SWL Store Word Left (cont.) SWL
TLB Modified exception (reserved)
SWR Store Word Right SWR
SWR Store Word Right (cont.) SWR
TLB Modified exception (reserved)
SYNC Synchronize SYNC
SYSCALL System Call SYSCALL
XOR Exclusive Or XOR
XORI Exclusive Or Immediate XORI
Bit Encoding of CPU Instruction Opcodes
Figure A-2 shows the bit codes for all CPU instructions (ISA and extended ISA). OPcode
Figure A-2. Operation Code Bit Encoding
SPECIAL function
BCOND
COPz rt
CP0 Function 2.0
Figure A-2. Operation Code Bit Encoding (cont)
MADD/MADDU
Notation :
Page
Page
Chapter 1 Introduction
1.1 Features
Page
1.2 Internal Blocks
Page
Chapter 2 Configuration
2.1 R3900 Processor Core
2.2 Clock Generator
2.3 Bus Interface Unit (Bus Controller / Write Buffer)
2.4 Address Protection Unit
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2.5 Debug Support Unit
2.6 Synchronizer
Figure 2-4 INT* signal synchronization
(3) NMI* The NMI* signal is synchronized with the processor clock in phase with SYSCLK (Figure 2-5).
Figure 2-5 NMI* signal synchronization
Figure 2-6 CPCOND* signal synchronization
Chapter 3 Pins
4.
Chapter 4 Operations
4.1 Clock
Page
4.2 Read Operation
Page
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Figure 4-3 Burst read (4 words : 1 wait)
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4.3 Write Operation
4.4 Interrupts
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4.5 Bus Arbitration
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4.6 Reset
4.7 Half-Speed Bus Mode
Chapter 5 Power-Down Mode
5.1 Halt mode
Page
5.2 Standby Mode
5.3 Doze Mode
5.4 Reduced Frequency Mode
