Architecture
102
ADD Add ADD
31 26 25 21 20 16 15 11 10 65 0
SPECIAL
000000 rs rt rd 0
00000
ADD
100000
6 5 5 5 5 6
Format :
ADD rd, rs, rt
Description :
Adds the contents of general-purpose registers rs and rt and puts the result in general-purpose
register rd. If carry-out bits 31 and 30 differ, a two's complement overflow exception is raised and
destination register rd is not modified.
Operation :
T: GPR[rd] ← GPR[rs] + GPR[rt]
Exceptions :
Overflow