
Architecture
Chapter 4 Pipeline Architecture
4.1 Overview
The R3900 Processor Core executes instructions in five pipeline stages (F: instruction fetch; D: decode; E:
execute; M: memory access; W: register
F : An instruction is fetched from the instruction cache.
D : The instruction is decoded. Contents of the
E: Arithmetic, logical and shift operations are performed. The execution of multiple/divide instructions is begun.
M : The data cache is accessed in the case of load and store instructions.
W : The result is written to a general register.
Each pipeline stage is executed in one clock cycle. When the pipeline is fully utilized, five instructions are executed at the same time, resulting in an average instruction execution rate of one instruction per cycle as illustrated in Figure
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F | D | E | M | W |
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| F | D | E | M | W |
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Figure 4-1. Pipeline stages for executing R3900 Processor Core instructions
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