Architecture
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4.5 Divide Instruction (DIV, DIVU)
The R3900 Processor Core performs division instructions in the division unit independently of the pipeline.
Division starts from the pipeline E stage and takes 35 cycles. Figure 4-6 shows an example of a divide
instruction.
Division in the division
unit
E1 E2 E3 E34 E35
div r5,r1 FDEMW
mflo r4 FDES ES ES ES E MW
Note :
When an MTHI, MTLO, DIV or DIVU instruction comes up for execution when a DIV or DIVU
instruction is already being executed in progress, the R3900 will stop the DIV or DIVU in progress
and will begin executing the MTHI, MTLO or new DIV or DIVU instruction.
The R3900 Processor Core will not halt execution of a DIV or DIVU instruction when an exception
occurs during its execution.
Division stops in Halt and Doze mode. It restarts when the R3900 returns from Halt or Doze mode.
4.6 Streaming
During a cache refill operation, the R3900 Processor Core can resume execution immediately after arrival of
necessary data or instruction in cache even though cache refill operation is not completed. This is referred to
as “streaming.”
5. Figure 4-6. Example of DIV instruction