Cache Refill, Cache refill | Toshiba TX39 instruction

Architecture

7.4 Cache Refill

A physical cache line in the R3900 Processor Core comprises 4 words for the instruction cache and 1 word for the data cache. The refill size can be designated independently of the line size. The refill size can be 4/8/16/32 words for the instruction cache, and 1/4/8/16/32 words for the data cache. In a burst read operation, data or instructions of the designated refill size are read. However, when the data cache refill size is set to one word (Config register DCBR = 0), a single read operation is performed.

Both caches are refilled from the head of the refill boundary.

Regardless of the refill size, tags are updated one physical line at a time.

4 words

Missed word

Refill size

Refill start word

Refill size boundary

(a) Instruction cache

1 word	Missed word

Refill start word	Refill size boundary

(b) Data cache

Figure 7-6. Cache refill

Additional explanation : If an instruction changing the cache configuration (MTC0 to modify the Config

register, or any CACHE instruction) is executed during a refill cycle, the new configuration takes effect after the refill cycle in progress is completed. Note that instruction cache invalidation is possible only while the instruction cache is disabled.

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Toshiba TX39 user manual Cache Refill, Cache refill

Contents

TX39 Family Core Architecture Page Toshiba Contents Memory location of exception vectors EPC Exception Program Counter register Coprocessor Unusable exception Appendix a Instruction Set Details Bus Interface Unit Bus Controller / Write Buffer 230 227Bus request and bus grant 227 Cache snoop 228 229 Architecture Architecture Introduction FeaturesHigh-performance Risc techniques Low power consumption Data notation Signal notationNotation Used in This Manual Mathematical notation Architecture Overview Architecture CPU registers Registers CP0 registers Exception program counter Reserved † Destination register 5 bits Instruction Set OverviewOperation code 6 bits Source register 5 bits Coprocessor Load/storeComputational Jump/branch ALU Immediate Computational InstructionsALU 3-operand, register type Special Instructions Multiply/DivideJump/Branch Instructions Coprocessor Instructions CP0 instructions Instruction Description CP0 Instructions Special Instruction Big endian and little endian formats Data Formats and Addressing Architecture Byte addresses of a misaligned word Pipeline Processing Overview 1 R3900 Processor Core operating modes User modeKernel mode Memory Management Unit MMU Kseg1 Direct segment mappingKuseg Kseg0 Address mapping Architecture Instruction Formats Instruction Set OverviewInstruction Notation Load and Store Instructions Byte specifications for load and store instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MTHI, Mtlo Instruction Format and Description MFHI, Mflo Instruction Format and Description Architecture Jump instructions Jump/Branch InstructionsInstruction Format and Description 10. Branch instructions Instruction in the delay slot is executed during the jump Architecture 11. Special instructions Special Instructions COPz Instruction Format and Description Coprocessor InstructionsBCzT, BCzF Instruction Format and Description Architecture Cache Instruction Format and Description Restore FromSystem Control Coprocessor CP0 Instructions 13. System control coprocessor CP0 instructions Pipeline Architecture Delayed load Delay SlotDelayed branching Nonblocking load function Nonblocking Load Function Streaming Divide Instruction DIV, Divu R3900 Processor Core Operating Modes Memory Management Unit MMU Internal MMU virtual address space Direct Segment Mapping Kuseg 512MB Exception Processing Utlb TLBL2 Cache register Exception Processing RegistersCause register Status register Bits Mnemonic Field name Description Cause register register no.13Read/Write Mnemonic Cause ExcCode field Read Status register register no.12Bits Field name Description Status register 1/2 Bits Mnemonic Field name Description Value on Read IntMask Interrupt Mask KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old NmI Non-maskable Interrupt Cache register Cache register register no.7 DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works PRId Processor Revision Identifier register register no.15 BadVAddr Bad Virtual Address register register no.8 21-19 Config Configuration register register no.3 10. Config register2/2 Exception Details ∙ Processing Address Error exception ∙ Causes∙ Exception mask ∙ Applicable instructions ∙ Servicing Breakpoint exception ∙ Cause Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Reserved Instruction exception ∙ Cause Overflow exception ∙ Cause Reset exception ∙ Cause Non-maskable interrupt ∙ Cause System Call exception ∙ Cause Architecture Return from Exception Handler Priority of ExceptionsPriority of Exceptions Exception Mnemonic Architecture Instruction Cache Caches Data Cache Data cache configuration Lock function Lock bit settingOperation during lock Auto-lock bits Lock bit clearing Example Cache Test FunctionCache disabling Cache flushing Cache refill Cache Refill Cache Snoop Architecture System Control Processor CP0 Registers Debugging Functions Depc †† PRId Processor revision ID Debug †† Debug exception control DM Debug Mode 0 at reset DBD Debug Branch DelayDebug register register no.16 OES Other Exceptions Status BsF Bus Error Exception FlagSSt Single at reset NIS Non-maskable Interrupt Status Debug Single Step DSS Debug ExceptionsDSS bit Types of debug exceptions Ii Debug exception handler execution Branching to a debug exception handler Executing a Deret instruction Iii Return from a debug exception handlerException priorities Single Step exception ∙ Cause Details of Debug Exceptions∙ Exception masking Debug Breakpoint exception ∙ Cause ∙ Instruction causing this exception Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Bitwise logical XOR operation Twos complement division Examples of Instruction Notation Function Meaning Table A-2. Common Load/Store Functions Byte access 8 bits Word access 32 bitsTriplebyte access 24 bits Halfword access 16 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Data Bit# Cache Name Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori Special function OPcodeCOPz rs CP0 Function COPz rt Notation TMPR3901F 200 On-chip peripheral circuits R3900 Processor CoreBus interface for ease of system implementation Package Low power consumption, optimal for portable applicationsDebugging support functions on chip Maximum operating frequency Address protection unit Internal BlocksR3900 Processor Core Clock generator Bus interface unit bus controller / write buffer 204 R3900 Processor Core ConfigurationInstruction Iimitations Address mapping Clock Generator Sync NOP Registers Break Address register BAddr0-1 Address Protection Unit Break Control register BCnt0-1 Break Mask register BMsk0-1 Memory protection exception Break Status register BSts BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 Debug Support UnitSynchronizer Register address map INT50 INT* signal synchronization NMI* signal synchronization CPCOND31 CPCOND* signal synchronization Pins Doze signal. Indicates that TMPR3901F is in doze mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Halt signal. Indicates that TMPR3901F is in halt mode ∙ Processor Clock OperationsClock ∙ Master Clock System clock Master clock ProcessorClock Single Read Read Operation Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Single write operation 2 waits Write Operation 1 NMI Interrupts Interrupt 2 INT50 Bus request and bus grant Bus Arbitration BUSGNT*L Reset Single read operation in half-speed bus mode Half-Speed Bus Mode Halt mode Power-Down Mode 232 Standby mode PLL stop Standby Mode Doze Mode Reduced Frequency Mode