Architecture
145
LB Load Byte LB
31 26 25 21 20 16 15 0
LB
100000 base rt offset
6 5 5 16
Format :

LB rt, offset(base)

Description :

Generates a 32-bit effective address by sign-extending the 16-bit offset and adding it to the contents

of general-purpose register base. It then sign-extends the byte at the memory location pointed to by

the effective address and loads the result into general-purpose register rt.

Operation :
T: vAddr ← ((offset15)16 || offset15..0) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr31..2 || (pAddr1..0 xor ReverseEndian2)
mem ← LoadMemory (uncached, BYTE, pAddr, vAddr, DATA)
byte ← vAddr1..0 xor BigEndianCPU2
GPR[rt] ←(mem7+8*byte)24 || mem7+8byte..8*byte
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)
Address Error exception