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Toshiba TX39 user manual Nor

Models: TX39

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Architecture

NOR

Nor

NOR

	31	26 25		21 20		16 15		11 10		6 5		0
		SPECIAL		rs		rt		rd		0		NOR
				rs		rt		rd
		000000								00000		100111
		6		5		5		5		5		6

Format :

NOR rd, rs, rt

Description :

Bitwise NORs the contents of general register rs with the contents of general register rt, and loads the result in general register rd.

Operation :

T:GPR[rd] ← GPR[rs] nor GPR[rt]

Exceptions :

None

168

Image 179

Toshiba TX39 user manual Nor

Contents

TX39 Family Core Architecture Page Toshiba Contents Memory location of exception vectors EPC Exception Program Counter registerCoprocessor Unusable exception Appendix a Instruction Set DetailsBus Interface Unit Bus Controller / Write Buffer 230 227Bus request and bus grant 227 Cache snoop 228 229Architecture Architecture High-performance Risc techniques FeaturesIntroduction Low power consumption Data notation Signal notationNotation Used in This Manual Mathematical notationArchitecture Overview ArchitectureCPU registers RegistersCP0 registers Exception program counter Reserved †Destination register 5 bits Instruction Set OverviewOperation code 6 bits Source register 5 bitsCoprocessor Load/storeComputational Jump/branchALU 3-operand, register type Computational InstructionsALU Immediate Special Instructions Multiply/DivideJump/Branch Instructions Coprocessor InstructionsCP0 instructions Instruction Description CP0 Instructions Special InstructionBig endian and little endian formats Data Formats and AddressingArchitecture Byte addresses of a misaligned word Pipeline Processing Overview 1 R3900 Processor Core operating modes User modeKernel mode Memory Management Unit MMUKseg1 Direct segment mappingKuseg Kseg0Address mapping Architecture Instruction Notation Instruction Set OverviewInstruction Formats Load and Store Instructions Byte specifications for load and store instructionsBase Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MTHI, Mtlo Instruction Format and Description MFHI, Mflo Instruction Format and DescriptionArchitecture Instruction Format and Description Jump/Branch InstructionsJump instructions 10. Branch instructions Instruction in the delay slot is executed during the jumpArchitecture 11. Special instructions Special InstructionsBCzT, BCzF Instruction Format and Description Coprocessor InstructionsCOPz Instruction Format and Description Architecture Cache Instruction Format and Description Restore FromSystem Control Coprocessor CP0 Instructions 13. System control coprocessor CP0 instructionsPipeline Architecture Delayed branching Delay SlotDelayed load Nonblocking load function Nonblocking Load FunctionStreaming Divide Instruction DIV, DivuR3900 Processor Core Operating Modes Memory Management Unit MMUInternal MMU virtual address space Direct Segment MappingKuseg 512MB Exception Processing Utlb TLBL2 Cache register Exception Processing RegistersCause register Status registerRead/Write Cause register register no.13Bits Mnemonic Field name Description Mnemonic Cause ExcCode fieldRead Status register register no.12Bits Field name DescriptionStatus register 1/2 Bits Mnemonic Field name Description Value on Read IntMask Interrupt Mask KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old NmI Non-maskable InterruptCache register Cache register register no.7DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works PRId Processor Revision Identifier register register no.15 BadVAddr Bad Virtual Address register register no.821-19 Config Configuration register register no.310. Config register2/2 Exception Details ∙ Processing Address Error exception ∙ Causes∙ Exception mask ∙ Applicable instructions∙ Servicing Breakpoint exception ∙ CauseBus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Reserved Instruction exception ∙ Cause Overflow exception ∙ CauseReset exception ∙ Cause Non-maskable interrupt ∙ Cause System Call exception ∙ CauseArchitecture Priority of Exceptions Exception Mnemonic Priority of ExceptionsReturn from Exception Handler Architecture Instruction Cache CachesData Cache Data cache configurationOperation during lock Lock bit settingLock function Auto-lock bits Lock bit clearingExample Cache Test FunctionCache disabling Cache flushingCache refill Cache RefillCache Snoop Architecture System Control Processor CP0 Registers Debugging FunctionsDepc †† PRId Processor revision ID Debug †† Debug exception controlDebug register register no.16 DBD Debug Branch DelayDM Debug Mode 0 at reset OES Other Exceptions Status BsF Bus Error Exception FlagSSt Single at reset NIS Non-maskable Interrupt StatusDebug Single Step DSS Debug ExceptionsDSS bit Types of debug exceptionsIi Debug exception handler execution Branching to a debug exception handlerException priorities Iii Return from a debug exception handlerExecuting a Deret instruction ∙ Exception masking Details of Debug ExceptionsSingle Step exception ∙ Cause Debug Breakpoint exception ∙ Cause ∙ Instruction causing this exceptionArchitecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Bitwise logical XOR operation Twos complement divisionExamples of Instruction Notation Function Meaning Table A-2. Common Load/Store FunctionsByte access 8 bits Word access 32 bitsTriplebyte access 24 bits Halfword access 16 bitsJump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Data Bit# Cache NameBit# Cache Operation Description Name CFCz COPz COPzCTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCzMFCz Mfhi Mflo MTC0 MTCz MTCzMthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori COPz rs OPcodeSpecial function CP0 Function COPz rtNotation TMPR3901F 200 Bus interface for ease of system implementation R3900 Processor CoreOn-chip peripheral circuits Package Low power consumption, optimal for portable applicationsDebugging support functions on chip Maximum operating frequencyAddress protection unit Internal BlocksR3900 Processor Core Clock generator Bus interface unit bus controller / write buffer204 Instruction Iimitations ConfigurationR3900 Processor Core Address mapping Clock GeneratorSync NOP Registers Break Address register BAddr0-1 Address Protection UnitBreak Control register BCnt0-1 Break Mask register BMsk0-1Memory protection exception Break Status register BStsBSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 Debug Support UnitSynchronizer Register address mapINT50 INT* signal synchronizationNMI* signal synchronization CPCOND31 CPCOND* signal synchronizationPins Doze signal. Indicates that TMPR3901F is in doze mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Halt signal. Indicates that TMPR3901F is in halt mode∙ Processor Clock OperationsClock ∙ Master ClockClock Master clock ProcessorSystem clock Single Read Read OperationBus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Single write operation 2 waits Write Operation1 NMI InterruptsInterrupt 2 INT50Bus request and bus grant Bus ArbitrationBUSGNT*L Reset Single read operation in half-speed bus mode Half-Speed Bus ModeHalt mode Power-Down Mode232 Standby mode PLL stop Standby ModeDoze Mode Reduced Frequency Mode