Pins | Toshiba TX39 instruction

TMPR3901F

Chapter 3 Pins

The following table summarizes the TMPR3901F pins.

NAME	I/O		DESCRIPTION

	I/O	Address bus. When TMPR3901F has bus mastership, outputs the address
A [31:2]		to be accessed. When TMPR3901F releases bus mastership, inputs the
		data cache snoop address.
	O	Byte-enable signal. At read and write, indicates which bytes of the data bus
		are accessed by TMPR3901F. The correspondence with the data bus is:
		BE [3]* : D [31:24]
BE [3:0]*		BE [2]* : D [23:16]
		BE [1]* : D [15:8]
		BE [0]* : D [7:0]
D [31:0]	I/O	Data bus.
RD*	O	Read signal. Indicates that a read operation is being executed.
WR*	O	Write signal. Indicates that a write operation is being executed.
LAST*	O	Last signal. Indicates the last data transfer of a bus operation. Please use
LAST*		this signal after sampling for the clock rising edge.
		this signal after sampling for the clock rising edge.
BSTART*	O	Bus start signal. Asserted for one clock only, at the start of a bus operation.
BSTART*		Please use this signal after sampling for the clock rising edge.

ACK*	I	Acknowledge signal. Used by external circuits to notify TMPR3901F that
ACK*		the bus cycle can be completed.
		the bus cycle can be completed.
BUSERR*	I	Bus error signal. Used by external circuits to notify TMPR3901F of an error
BUSERR*		in a read bus operation.
		in a read bus operation.
BURST*	O	Burst signal. Indicates that a burst-read operation is being executed.
	O	Burst size signal. Indicates the number of words to be read in a burst-read
		operation.
BSTSZ [1:0]		BSTSZ[1]	BSTSZ[0]	No. of Word
BSTSZ [1:0]		L	L	4
		L	L	4
		L	H	8
		H	L	16
		H	H	32

	I	Snoop signal. Used by external circuits to instruct snooping of the
SNOOP*		TMPR3901F internal data cache. When the SNOOP* signal is asserted, if
SNOOP*		the address on A[31:2] hits the data in the data cache, TMPR3901F

		invalidates the data.
BUSREQ*	I	BUS request signal. Issued by an external bus master to request bus
BUSREQ*		mastership from TMPR3901F.
		mastership from TMPR3901F.

*Active-low signal

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Image 226

Toshiba TX39 user manual Pins

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 229 227Bus request and bus grant 227 Cache snoop 228 230 Architecture Architecture Introduction FeaturesHigh-performance Risc techniques Low power consumption Mathematical notation Signal notationNotation Used in This Manual Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Source register 5 bits Instruction Set OverviewOperation code 6 bits Destination register 5 bits Jump/branch Load/storeComputational Coprocessor ALU Immediate Computational InstructionsALU 3-operand, register type Coprocessor Instructions Multiply/DivideJump/Branch Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview Memory Management Unit MMU User modeKernel mode 1 R3900 Processor Core operating modes Kseg0 Direct segment mappingKuseg Kseg1 Address mapping Architecture Instruction Formats Instruction Set OverviewInstruction Notation Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Jump instructions Jump/Branch InstructionsInstruction Format and Description Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions COPz Instruction Format and Description Coprocessor InstructionsBCzT, BCzF Instruction Format and Description Architecture 13. System control coprocessor CP0 instructions Restore FromSystem Control Coprocessor CP0 Instructions Cache Instruction Format and Description Pipeline Architecture Delayed load Delay SlotDelayed branching Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Status register Exception Processing RegistersCause register Cache register Bits Mnemonic Field name Description Cause register register no.13Read/Write ExcCode field Mnemonic Cause Field name Description Status register register no.12Bits Read Status register 1/2 Bits Mnemonic Field name Description Value on Read NmI Non-maskable Interrupt KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details ∙ Applicable instructions Address Error exception ∙ Causes∙ Exception mask ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Return from Exception Handler Priority of ExceptionsPriority of Exceptions Exception Mnemonic Architecture Caches Instruction Cache Data cache configuration Data Cache Lock function Lock bit settingOperation during lock Lock bit clearing Auto-lock bits Cache flushing Cache Test FunctionCache disabling Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† DM Debug Mode 0 at reset DBD Debug Branch DelayDebug register register no.16 NIS Non-maskable Interrupt Status BsF Bus Error Exception FlagSSt Single at reset OES Other Exceptions Status Types of debug exceptions Debug ExceptionsDSS bit Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Executing a Deret instruction Iii Return from a debug exception handlerException priorities Single Step exception ∙ Cause Details of Debug Exceptions∙ Exception masking ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Halfword access 16 bits Word access 32 bitsTriplebyte access 24 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori Special function OPcodeCOPz rs COPz rt CP0 Function Notation TMPR3901F 200 On-chip peripheral circuits R3900 Processor CoreBus interface for ease of system implementation Maximum operating frequency Low power consumption, optimal for portable applicationsDebugging support functions on chip Package Bus interface unit bus controller / write buffer Internal BlocksR3900 Processor Core Clock generator Address protection unit 204 R3900 Processor Core ConfigurationInstruction Iimitations Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Register address map Debug Support UnitSynchronizer BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Halt signal. Indicates that TMPR3901F is in halt mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Doze signal. Indicates that TMPR3901F is in doze mode ∙ Master Clock OperationsClock ∙ Processor Clock System clock Master clock ProcessorClock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode