TMPR3901F
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Chapter 3 Pins
The following table summarizes the TMPR3901F pins.
NAME I/O DESCRIPTION
A [31:2] I/O Address bus. When TMPR3901F has bus mastership, outputs the address
to be accessed. When TMPR3901F releases bus mastership, inputs the
data cache snoop address.
BE [3:0]*
OByte-enable signal. At read and write, indicates which bytes of the data bus
are accessed by TMPR3901F. The correspondence with the data bus is:
BE [3]* : D [31:24]
BE [2]* : D [23:16]
BE [1]* : D [15:8]
BE [0]* : D [7:0]
D [31:0] I/O Data bus.
RD* ORead signal. Indicates that a read operation is being executed.
WR* OWrite signal. Indicates that a write operation is being executed.
LAST* OLast signal. Indicates the last data transfer of a bus operation. Please use
this signal after sampling for the clock rising edge.
BSTART* OBus start signal. Asserted for one clock only, at the start of a bus operation.
Please use this signal after sampling for the clock rising edge.
ACK* IAcknowledge signal. Used by external circuits to notify TMPR3901F that
the bus cycle can be completed.
BUSERR* IBus error signal. Used by external circuits to notify TMPR3901F of an error
in a read bus operation.
BURST* OBurst signal. Indicates that a burst-read operation is being executed.
BSTSZ [1:0]
OBurst size signal. Indicates the number of words to be read in a burst-read
operation.
SNOOP*
ISnoop signal. Used by external circuits to instruct snooping of the
TMPR3901F internal data cache. When the SNOOP* signal is asserted, if
the address on A[31:2] hits the data in the data cache, TMPR3901F
invalidates the data.
BUSREQ* IBUS request signal. Issued by an external bus master to request bus
mastership from TMPR3901F.
* Active-low signal
BSTSZ[1] BSTSZ[0] No. of Word
L L 4
LH8
HL 16
H H 32