Architecture
29
Table 3-6. Shift instructions
(a) SLL, SRL, SRA
Instruction Format and Description
Shift Left
Logical SLL rd, rt, sa
Left-shift the contents of register rt by the number of bits indicated in sa (shift
amount), and zero-fill the low-order bits. Store the resulting 32 bits in register
rd.
Shift Right
Logical SRL rd, rt, sa
Right-shift the contents of register rt by sa bits, and zero-fill the high-order bits.
Store the resulting 32 bits in register rd.
Shift Right
Arithmetic SRA rd, rt, sa
Right-shift the contents of register rt by sa bits, and sign-extend the high-order
bits. Store the resulting 32 bits in register rd.
(b) SLLV, SRLV, SRAV
Instruction Format and Description
Shift Left
Logical
Variable
SLLV rd, rt, sa
Left-shift the contents of register rt. The number of bits shifted is indicated in
the 5 low-order bits of the register rs contents. Zero-fill the low-order bits of rt
and store the resulting 32 bits in register rd.
Shift Right
Logical
Variable
SRLV rd, rt, sa
Right-shift the contents of register rt. The number of bits shifted is indicated in
the 5 low-order bits of the register rs contents. Zero-fill the high-order bits of rt
and store the resulting 32 bits in register rd.
Shift Right
Arithmetic
Variable
SRAV rd, rt, sa
Right-shift the contents of register rt. The number of bits shifted is indicated in
the 5 low-order bits of the register rs contents. Sign-extend the high-order bits
of rt and store the resulting 32 bits in register rd.
rt
rt
0
rs
funct
funct
sa
0
op
op
rd
rd