Architecture
95
Instruction Formats
Every instruction consists of a single word (32 bits) aligned on a word boundary. The main instruction
formats are shown in Figure A-1.
31 26 25 21 20 16 15 0
op rs rt immediate
31 26 25 0
op target
31 26 25 21 20 16 15 11 10 6 5 0
op rs rt rd sa funct
op Operation code (6 bits)
rs Source register (5 bits)
rt Target (source or destination) register, or branch condition (5 bits)
rd Destination register (5 bits)
immediate Immediate, branch displacement, address displacement (16 bits)
target Branch target address (26 bits)
sa Shift amount (5 bits)
funct Function (6 bits)
Figure A-1. CPU Instruction Formats
I-type (Immediate)
J-type (Jump)
R-type (Register)