Toshiba TX39 user manual Twos complement division, Bitwise logical XOR operation

Architecture

Table A-1. Symbols used in instruction operation notation

Symbol	Meaning
←	Assignment
	Bit string concatenation
xy	Replication of bit value x into a y-bit string.	Note that x is always a single-bit value.
xy..z	Selection of bits y through z of bit string x.	Little endian bit notation is always used
	here. If y is less than z, this expression results in an empty (null length) bit string.
+	Two's complement addition
-	Two's complement subtraction
*	Two's complement multiplication
div	Two's complement division
mod	Two's complement modulo
<	Two's complement "less than" comparison
and	Bitwise logical AND operation
or	Bitwise logical OR operation
xor	Bitwise logical XOR operation
nor	Bitwise logical NOR operation
GPR [x]	General-purpose register x. The content of GPR[0] is always 0, and attempting to
	change this content has no effect.
CPR [z,x]	General-purpose register x of coprocessor unit z
CCR [z,x]	Control register x of coprocessor unit z
COC [z]	Condition signal of coprocessor unit z
BigEndian	Big endian mode as configured at reset (0: little; 1: big). This determines the which
Mem	endian format is used with the memory interface (see Load Memory and Store Memory)
	and with kernel mode execution.
Reverse	A signal to reverse the endian format of load and store instructions.		This function can
Endian	be used only in user mode. The endian format is reversed by setting the Status
	register RE bit. Accordingly, ReverseEndian can be computed as (RE bit AND user
	mode).
BigEndian	The endian format for load and store instructions (0: little; 1: big).		In user mode, the
CPU	endian format is reversed by setting the RE bit. Accordingly, BigEndianCPU can be
	computed as BigEndianMem XOR ReverseEndian.
T + i:	This indicates the time steps between operations. Statements within a time step are
	defined to execute in sequential order, as modified by condition and rule structures. An
	operation marked by T + i: is executed at instruction cycle i relative to the start of the
	instruction's execution. For example, an instruction starting at time j executes
	operations marked T + i: at time i + j. The order is not defined for two instructions or
	two operations executing at the same time.
vAddress	Virtual address
pAddress	Physical address

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