Architecture
191
SWR Store Word Right (cont.) SWR
Operation :
T: vAddr ← ((offset15)16 || offset15..0) + GPR[base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr31..2 || (pAddr1..0 xor ReverseEndian2)
If BigEndianMem = 0 then
pAddr ← pAddr31..2 || 02
endif
byte ← vAddr1..0 xor BigEndianCPU2
data ← GPR[rt]31-8*byte || 08*byte
StoreMemory (uncached, WORD-byte, data, pAddr, vAddr, DATA)
Exceptions :
UTLB Refill exception (reserved)
TLB Refill exception (reserved)

TLB Modified exception (reserved)

Address Error exception