Architecture
134
CACHE Cache (cont.) CACHE
Bits 20..18 of the Cache instruction select the operation to be performed as follows.
Bit# Cache Operation Description
20 19 18 ID Name
000 IIndexInvalidate Sets the cache state of the cache block to
Invalid. This instruction is valid only
when the instruction cache is invalid
(Config register ICE bit is 0).
001 DIndexLRUBitClear Clears the LRU bit of the cache at the
designated index.
010 DIndexLockBitClear Clears the Lock bit of the cache at the
designated index.
100 DHitInvalidate If a cache block contains the designated
address, sets that cache block to Invalid.
Operation :
T: vAddr ← ((offset15)16 || offset15..0) + GPR[base]
(pAddr, uncached ← AddressTranslation (vAddr, DATA)
Exceptions :
Coprocessor Unusable exception