Introduction, Features | Toshiba TX39 instruction

Architecture

Chapter 1 Introduction

1.1 Features

The R3900 Processor Core is a high-performance 32-bit microprocessor core developed by Toshiba based on the R3000A RISC (Reduced Instruction Set Computer) microprocessor. The R3000A was developed by MIPS Technologies, Inc.

Toshiba develops ASSPs (Application Specific Standard Products) using the R3900 Processor Core and provides the R3900 as a processor core in Embedded Array or Cell-based ICs. The low power consumption and high cost-performance ratio of this processor make it especially well-suited to embedded control applications in products such as PDAs (Personal Digital Assistants) and game equipment.

1.1.1High-performance RISC techniques

∙R3000A architecture

−R3000A upward compatible instruction set (excluding TLB (translation lookaside buffer) instructions and some coprocessor instructions)

−Five-stage pipeline

∙Built-in cache memory

−Separate instruction and data caches

−Data cache snoop function: Invalidatation of data in the data cache to maintain cache memory and main memory consistency on DMA transfer cycles

∙Nonblocking load

−Execute the following instruction regardless of a cache miss caused by a preceding load instruction

∙DSP function

−Multiply/Add (32-bit x 32-bit + 64-bit) in one clock cycle.

1.1.2Functions for embedded applications

∙Small code size

−Branch Likely instruction:The branch delay slot accepts an instruction to be executed at the branch target

−Hardware Interlock: Stall the pipeline at the load delay slot when the instruction in the slot depends on the data to be loaded

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Toshiba TX39 user manual Introduction, Features, High-performance Risc techniques

Contents

TX39 Family Core Architecture Page Toshiba Contents Memory location of exception vectors EPC Exception Program Counter register Coprocessor Unusable exception Appendix a Instruction Set Details Bus Interface Unit Bus Controller / Write Buffer 230 227Bus request and bus grant 227 Cache snoop 228 229 Architecture Architecture High-performance Risc techniques FeaturesIntroduction Low power consumption Data notation Signal notationNotation Used in This Manual Mathematical notation Architecture Overview Architecture CPU registers Registers CP0 registers Exception program counter Reserved † Destination register 5 bits Instruction Set OverviewOperation code 6 bits Source register 5 bits Coprocessor Load/storeComputational Jump/branch ALU 3-operand, register type Computational InstructionsALU Immediate Special Instructions Multiply/DivideJump/Branch Instructions Coprocessor Instructions CP0 instructions Instruction Description CP0 Instructions Special Instruction Big endian and little endian formats Data Formats and Addressing Architecture Byte addresses of a misaligned word Pipeline Processing Overview 1 R3900 Processor Core operating modes User modeKernel mode Memory Management Unit MMU Kseg1 Direct segment mappingKuseg Kseg0 Address mapping Architecture Instruction Notation Instruction Set OverviewInstruction Formats Load and Store Instructions Byte specifications for load and store instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MTHI, Mtlo Instruction Format and Description MFHI, Mflo Instruction Format and Description Architecture Instruction Format and Description Jump/Branch InstructionsJump instructions 10. Branch instructions Instruction in the delay slot is executed during the jump Architecture 11. Special instructions Special Instructions BCzT, BCzF Instruction Format and Description Coprocessor InstructionsCOPz Instruction Format and Description Architecture Cache Instruction Format and Description Restore FromSystem Control Coprocessor CP0 Instructions 13. System control coprocessor CP0 instructions Pipeline Architecture Delayed branching Delay SlotDelayed load Nonblocking load function Nonblocking Load Function Streaming Divide Instruction DIV, Divu R3900 Processor Core Operating Modes Memory Management Unit MMU Internal MMU virtual address space Direct Segment Mapping Kuseg 512MB Exception Processing Utlb TLBL2 Cache register Exception Processing RegistersCause register Status register Read/Write Cause register register no.13Bits Mnemonic Field name Description Mnemonic Cause ExcCode field Read Status register register no.12Bits Field name Description Status register 1/2 Bits Mnemonic Field name Description Value on Read IntMask Interrupt Mask KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old NmI Non-maskable Interrupt Cache register Cache register register no.7 DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works PRId Processor Revision Identifier register register no.15 BadVAddr Bad Virtual Address register register no.8 21-19 Config Configuration register register no.3 10. Config register2/2 Exception Details ∙ Processing Address Error exception ∙ Causes∙ Exception mask ∙ Applicable instructions ∙ Servicing Breakpoint exception ∙ Cause Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Reserved Instruction exception ∙ Cause Overflow exception ∙ Cause Reset exception ∙ Cause Non-maskable interrupt ∙ Cause System Call exception ∙ Cause Architecture Priority of Exceptions Exception Mnemonic Priority of ExceptionsReturn from Exception Handler Architecture Instruction Cache Caches Data Cache Data cache configuration Operation during lock Lock bit settingLock function Auto-lock bits Lock bit clearing Example Cache Test FunctionCache disabling Cache flushing Cache refill Cache Refill Cache Snoop Architecture System Control Processor CP0 Registers Debugging Functions Depc †† PRId Processor revision ID Debug †† Debug exception control Debug register register no.16 DBD Debug Branch DelayDM Debug Mode 0 at reset OES Other Exceptions Status BsF Bus Error Exception FlagSSt Single at reset NIS Non-maskable Interrupt Status Debug Single Step DSS Debug ExceptionsDSS bit Types of debug exceptions Ii Debug exception handler execution Branching to a debug exception handler Exception priorities Iii Return from a debug exception handlerExecuting a Deret instruction ∙ Exception masking Details of Debug ExceptionsSingle Step exception ∙ Cause Debug Breakpoint exception ∙ Cause ∙ Instruction causing this exception Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Bitwise logical XOR operation Twos complement division Examples of Instruction Notation Function Meaning Table A-2. Common Load/Store Functions Byte access 8 bits Word access 32 bitsTriplebyte access 24 bits Halfword access 16 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Data Bit# Cache Name Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori COPz rs OPcodeSpecial function CP0 Function COPz rt Notation TMPR3901F 200 Bus interface for ease of system implementation R3900 Processor CoreOn-chip peripheral circuits Package Low power consumption, optimal for portable applicationsDebugging support functions on chip Maximum operating frequency Address protection unit Internal BlocksR3900 Processor Core Clock generator Bus interface unit bus controller / write buffer 204 Instruction Iimitations ConfigurationR3900 Processor Core Address mapping Clock Generator Sync NOP Registers Break Address register BAddr0-1 Address Protection Unit Break Control register BCnt0-1 Break Mask register BMsk0-1 Memory protection exception Break Status register BSts BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 Debug Support UnitSynchronizer Register address map INT50 INT* signal synchronization NMI* signal synchronization CPCOND31 CPCOND* signal synchronization Pins Doze signal. Indicates that TMPR3901F is in doze mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Halt signal. Indicates that TMPR3901F is in halt mode ∙ Processor Clock OperationsClock ∙ Master Clock Clock Master clock ProcessorSystem clock Single Read Read Operation Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Single write operation 2 waits Write Operation 1 NMI Interrupts Interrupt 2 INT50 Bus request and bus grant Bus Arbitration BUSGNT*L Reset Single read operation in half-speed bus mode Half-Speed Bus Mode Halt mode Power-Down Mode 232 Standby mode PLL stop Standby Mode Doze Mode Reduced Frequency Mode