
Architecture
Chapter 1 Introduction
1.1 Features
The R3900 Processor Core is a
Toshiba develops ASSPs (Application Specific Standard Products) using the R3900 Processor Core and provides the R3900 as a processor core in Embedded Array or
1.1.1High-performance RISC techniques
∙R3000A architecture
−R3000A upward compatible instruction set (excluding TLB (translation lookaside buffer) instructions and some coprocessor instructions)
−
∙
−Separate instruction and data caches
−Data cache snoop function: Invalidatation of data in the data cache to maintain cache memory and main memory consistency on DMA transfer cycles
∙Nonblocking load
−Execute the following instruction regardless of a cache miss caused by a preceding load instruction
∙DSP function
−Multiply/Add
1.1.2Functions for embedded applications
∙Small code size
−Branch Likely instruction:The branch delay slot accepts an instruction to be executed at the branch target
−Hardware Interlock: Stall the pipeline at the load delay slot when the instruction in the slot depends on the data to be loaded
3