Toshiba TX39 Connect to crystal oscillator, Stops internal PLL oscillation, Or low, Big endian

TMPR3901F

NAME	I/O	DESCRIPTION
BUSGNT*	O	Bus grant signal. Used by TMPR3901F to indicate it has released bus
		mastership in response to a request by an external bus master.
XIN	I	Connect to crystal oscillator.
XOUT	O	Connect to crystal oscillator.
PLLOFF*	I	Stops internal PLL oscillation.
CLKEN	I	Enables internal PLL clock.
	O	System clock signal. TMPR3901F bus operation is based on SYSCLK. The
SYSCLK		frequency can be reduced by 1/2, 1/4 or 1/8 using reduced frequency mode.
FCLK	O	Free clock signal. Outputs master clock independent of reduced frequency
		mode (quadruple frequency of crystal oscillator).
FCLKEN	I	Free clock enable signal. Specifies whether or not to output FCLK. Tie high
		or low.
RESET*	I	Reset signal. When asserted for at least 12 SYSCLK, resets TMPR3901F.
NMI*	I	Non-maskable interrupt signal. On transition from high to low,
		TMPR3901F generates a non-maskable interrupt.
INT[5:0]*	I	Interrupt signals. At low, TMPR3901F acknowledges as external interrupt.
		Keep low until TMPR3901F starts interrupt handling.
HALT	O	Halt signal. Indicates that TMPR3901F is in halt mode.
DOZE	O	Doze signal. Indicates that TMPR3901F is in doze mode.
ENDIAN	I	Endian signal. Tie high or low.
		H: Big endian
		L: Little endian.
HALF*	I	Bus divider signal. When low, bus operates at half frequency of system
		clock (SYSCLK). Tie high or low.
CPCOND	I	Coprocessor condition signal. Condition signal for coprocessor branch
[3:1]		instruction.
DCLK
PCST [2:0]
DSA0/TPC	−	Real-time debugger interface. Connect real-time debugger, or leave these
DBGE		signals open.
SDI/DINT
DRESET
TEST [4:0]	−	Test signals. Leave these signals open.
VDD	−	Connect to power supply.
VDD (for PLL)	−	Connect to power supply. Keep away from other VDD.
VSS	−	Connect to ground.
VSS (for PLL)	−	Connect to power supply. Keep away from other VSS.

*Active-low signal

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