TMPR3901F
216
NAME I/O DESCRIPTION
BUSGNT* OBus grant signal. Used by TMPR3901F to indicate it has released bus
mastership in response to a request by an external bus master.
XIN IConnect to crystal oscillator.
XOUT OConnect to crystal oscillator.
PLLOFF* IStops internal PLL oscillation.
CLKEN IEnables internal PLL clock.
SYSCLK OSystem clock signal. TMPR3901F bus operation is based on SYSCLK. The
frequency can be reduced by 1/2, 1/4 or 1/8 using reduced frequency mode.
FCLK OFree clock signal. Outputs master clock independent of reduced frequency
mode (quadruple frequency of crystal oscillator).
FCLKEN IFree clock enable signal. Specifies whether or not to output FCLK. Tie high
or low.
RESET* IReset signal. When asserted for at least 12 SYSCLK, resets TMPR3901F.
NMI* INon-maskable interrupt signal. On transition from high to low,
TMPR3901F generates a non-maskable interrupt.
INT[5:0]* IInterrupt signals. At low, TMPR3901F acknowledges as external interrupt.
Keep low until TMPR3901F starts interrupt handling.
HALT OHalt signal. Indicates that TMPR3901F is in halt mode.
DOZE ODoze signal. Indicates that TMPR3901F is in doze mode.
ENDIAN IEndian signal. Tie high or low.
H: Big endian
L: Little endian.
HALF* IBus divider signal. When low, bus operates at half frequency of system
clock (SYSCLK). Tie high or low.
CPCOND
[3:1] ICoprocessor condition signal. Condition signal for coprocessor branch
instruction.
DCLK
PCST [2:0]
DSA0/TPC
DBGE
SDI/DINT
DRESET
−Real-time debugger interface. Connect real-time debugger, or leave these
signals open.
TEST [4:0] −Test signals. Leave these signals open.
VDD −Connect to power supply.
VDD (for PLL) −Connect to power supply. Keep away from other VDD.
VSS −Connect to ground.
VSS (for PLL)−Connect to power supply. Keep away from other VSS.
* Active-low signal
4.