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Toshiba TX39 user manual Bltz

Models: TX39

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Architecture

BLTZ

Branch On Less Than Zero

BLTZ

	31	26 25		21 20		16 15		0
		BCOND		rs		BLTZ		offset
				rs				offset
		000001				00000
		6		5		5		16

Format :

BLTZ rs, offset

Description :

Generates a branch target address by adding the address of the instruction in the delay slot to the 16- bit offset (that has been left-shifted two bits and sign-extended to 32 bits). If the value in general- purpose register rs is negative (i.e., the sign bit of rs is 1), the program branches to the target address after a one-cycle delay.

Operation :

T:	target ← (offset )14	offset 02
	15
	condition ← (GPR[rs]31 = 1)
T + 1:	if condition then

PC ← PC + target

endif

Exceptions :

None

126

Image 137

Toshiba TX39 user manual Bltz

Contents

TX39 Family Core Architecture Page Toshiba Contents Memory location of exception vectors EPC Exception Program Counter registerCoprocessor Unusable exception Appendix a Instruction Set DetailsBus Interface Unit Bus Controller / Write Buffer Bus request and bus grant 227 Cache snoop 228 227229 230Architecture Architecture High-performance Risc techniques FeaturesIntroduction Low power consumption Notation Used in This Manual Signal notationMathematical notation Data notationArchitecture Overview ArchitectureCPU registers RegistersCP0 registers Exception program counter Reserved †Operation code 6 bits Instruction Set OverviewSource register 5 bits Destination register 5 bitsComputational Load/storeJump/branch CoprocessorALU 3-operand, register type Computational InstructionsALU Immediate Jump/Branch Instructions Multiply/DivideCoprocessor Instructions Special InstructionsCP0 instructions Instruction Description CP0 Instructions Special InstructionBig endian and little endian formats Data Formats and AddressingArchitecture Byte addresses of a misaligned word Pipeline Processing Overview Kernel mode User modeMemory Management Unit MMU 1 R3900 Processor Core operating modesKuseg Direct segment mappingKseg0 Kseg1Address mapping Architecture Instruction Notation Instruction Set OverviewInstruction Formats Load and Store Instructions Byte specifications for load and store instructionsBase Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MTHI, Mtlo Instruction Format and Description MFHI, Mflo Instruction Format and DescriptionArchitecture Instruction Format and Description Jump/Branch InstructionsJump instructions 10. Branch instructions Instruction in the delay slot is executed during the jumpArchitecture 11. Special instructions Special InstructionsBCzT, BCzF Instruction Format and Description Coprocessor InstructionsCOPz Instruction Format and Description Architecture System Control Coprocessor CP0 Instructions Restore From13. System control coprocessor CP0 instructions Cache Instruction Format and DescriptionPipeline Architecture Delayed branching Delay SlotDelayed load Nonblocking load function Nonblocking Load FunctionStreaming Divide Instruction DIV, DivuR3900 Processor Core Operating Modes Memory Management Unit MMUInternal MMU virtual address space Direct Segment MappingKuseg 512MB Exception Processing Utlb TLBL2 Cause register Exception Processing RegistersStatus register Cache registerRead/Write Cause register register no.13Bits Mnemonic Field name Description Mnemonic Cause ExcCode fieldBits Status register register no.12Field name Description ReadStatus register 1/2 Bits Mnemonic Field name Description Value on Read IEc/IEp/IEo Interrupt Enable current/previous/old KUc/KUp/KUo Kernel/User mode current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt MaskCache register Cache register register no.7DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works PRId Processor Revision Identifier register register no.15 BadVAddr Bad Virtual Address register register no.821-19 Config Configuration register register no.310. Config register2/2 Exception Details ∙ Exception mask Address Error exception ∙ Causes∙ Applicable instructions ∙ Processing∙ Servicing Breakpoint exception ∙ CauseBus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Reserved Instruction exception ∙ Cause Overflow exception ∙ CauseReset exception ∙ Cause Non-maskable interrupt ∙ Cause System Call exception ∙ CauseArchitecture Priority of Exceptions Exception Mnemonic Priority of ExceptionsReturn from Exception Handler Architecture Instruction Cache CachesData Cache Data cache configurationOperation during lock Lock bit settingLock function Auto-lock bits Lock bit clearingCache disabling Cache Test FunctionCache flushing ExampleCache refill Cache RefillCache Snoop Architecture System Control Processor CP0 Registers Debugging FunctionsDepc †† PRId Processor revision ID Debug †† Debug exception controlDebug register register no.16 DBD Debug Branch DelayDM Debug Mode 0 at reset SSt Single at reset BsF Bus Error Exception FlagNIS Non-maskable Interrupt Status OES Other Exceptions StatusDSS bit Debug ExceptionsTypes of debug exceptions Debug Single Step DSSIi Debug exception handler execution Branching to a debug exception handlerException priorities Iii Return from a debug exception handlerExecuting a Deret instruction ∙ Exception masking Details of Debug ExceptionsSingle Step exception ∙ Cause Debug Breakpoint exception ∙ Cause ∙ Instruction causing this exceptionArchitecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Bitwise logical XOR operation Twos complement divisionExamples of Instruction Notation Function Meaning Table A-2. Common Load/Store FunctionsTriplebyte access 24 bits Word access 32 bitsHalfword access 16 bits Byte access 8 bitsJump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Data Bit# Cache NameBit# Cache Operation Description Name CFCz COPz COPzCTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCzMFCz Mfhi Mflo MTC0 MTCz MTCzMthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori COPz rs OPcodeSpecial function CP0 Function COPz rtNotation TMPR3901F 200 Bus interface for ease of system implementation R3900 Processor CoreOn-chip peripheral circuits Debugging support functions on chip Low power consumption, optimal for portable applicationsMaximum operating frequency PackageR3900 Processor Core Clock generator Internal BlocksBus interface unit bus controller / write buffer Address protection unit204 Instruction Iimitations ConfigurationR3900 Processor Core Address mapping Clock GeneratorSync NOP Registers Break Address register BAddr0-1 Address Protection UnitBreak Control register BCnt0-1 Break Mask register BMsk0-1Memory protection exception Break Status register BStsSynchronizer Debug Support UnitRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1INT50 INT* signal synchronizationNMI* signal synchronization CPCOND31 CPCOND* signal synchronizationPins Mode quadruple frequency of crystal oscillator Enables internal PLL clockHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze modeClock Operations∙ Master Clock ∙ Processor ClockClock Master clock ProcessorSystem clock Single Read Read OperationBus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Single write operation 2 waits Write Operation1 NMI InterruptsInterrupt 2 INT50Bus request and bus grant Bus ArbitrationBUSGNT*L Reset Single read operation in half-speed bus mode Half-Speed Bus ModeHalt mode Power-Down Mode232 Standby mode PLL stop Standby ModeDoze Mode Reduced Frequency Mode