Toshiba TX39 Cause register register no.13, Bits Mnemonic Field name Description, Read/Write

Architecture

6.2.1Cause register (register no.13)

31	30	29	28 27		16 15		10 9		8 7		6	2	1	0
BD	0	CE[1:0]		0		IP[5:0]		Sw[1:0]		0	ExCode			0
1	1	2	12		6		2		1		5			2

Bits	Mnemonic	Field name	Description	Value on Reset	Read/Write
31	BD	Branch	Set to 1 when the most recent	Undefined	Read
		Delay	exception was caused by an
			instruction in the branch delay slot
			(executed during a branch).
29-28	CE	Coprocessor	Indicates the coprocessor unit	Undefined	Read
		Error	number referenced when a
			Coprocessor Unusable exception is
			raised. (CE1, CE0)
			(0, 0) = coprocessor unit no. 0
			(0, 1) = coprocessor unit no. 1
			(1, 0) = coprocessor unit no. 2
			(1, 1) = coprocessor unit no. 3
15-10	IP	Interrupt	Indicates a held external interrupt.	Undefined	Read
		Pending	The status of the external interrupt
			signal line is shown.
9-8	Sw	Software	Indicates a held software interrupt.	Undefined	Read/Write
		Interrupt	This field can be written in order to
			set or reset a software interrupt.
6-2	ExcCode	Exception	Holds an exception code (ExcCode)	Undefined	Read
		Code	indicating the cause of an exception.
			The causes corresponding to each
			exception code are shown in Table
			6-3.
30	0		Ignored on write; zero when read.	0	Read
27-16
7
1-0

For active interrupt signals, the corresponding IP bit is set to 1. For inactive interrupt signals, the IP bit is cleared to 0. The IP bit indicates the interrupt signal directly, independent of the Status register IEc bit and IntMask bit.

Figure 6-2. Cause register

51