Architecture

3.8 System Control Coprocessor (CP0) Instructions

Coprocessor 0 instructions are used for operations involving the system control coprocessor (CP0)registers, processor memory management and exception handling.

Note :Attempting to execute a CP0 instruction in user mode when the CU0 bit in the status register is not set will return a Coprocessor Unusable exception.

Table 3-13. System control coprocessor (CP0) instructions

 

 

 

(a)

MTC0, MFC0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Format and Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

op

funct

 

rt

 

rd

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Move To CP0

MTC0 rt, rd

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Move the contents of CPU general register rt to CP0 coprocessor register rd.

Move From

MFC0 rt, rd

 

 

 

 

 

 

 

 

 

 

 

 

 

CP0

Move the contents of CP0 coprocessor register rd to CPU general register rt.

 

(b)

RFE, DERET

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Format and Description

 

 

 

 

 

 

 

 

 

 

 

 

 

op

co

 

 

 

 

0

 

 

funct

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Restore From

RFE

 

 

 

 

 

 

 

 

 

 

 

 

 

Exception

Restore the previous mode bit of the Status register and Cache register into the

 

corresponding current mode bit, and restore the old status bit into the

 

corresponding previous mode bit.

 

 

 

 

 

 

 

 

 

 

 

Debug

DERET

 

 

 

 

 

 

 

 

 

 

 

 

 

Exception

Branch to the value in the CP0 DEPC register.

 

 

 

 

 

 

 

 

Return

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c) CACHE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

Format and Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

op

base

 

 

op

 

 

offset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cache

CACHE op, offset (base)

 

 

 

 

 

 

 

 

 

 

 

 

 

Operation

Add the contents of the CPU general registers designated by base and offset to

 

generate a virtual address. The MMU translates this virtual address to a

 

physical address. The cache operation to be performed at this address is

 

contained in op.

 

 

 

 

 

 

 

 

 

 

 

 

 

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Toshiba TX39 System Control Coprocessor CP0 Instructions, System control coprocessor CP0 instructions, Restore From