Toshiba TX39 user manual Bus error during a single read operation

TMPR3901F

At the start of a single read, the BSTART* signal is asserted for one clock cycle only. At the same time the RD* and LAST* signals are asserted. Then the address A[31:2] and BE[3:0]* signals are valid.

An external circuit drives the data onto the data bus and asserts an ACK* signal. The TMPR3901F samples the ACK* signal at the rising edge of SYSCLK, confirming that it has been asserted, and latches the data at the rising edge of the next clock.

The LAST* signal is de-asserted in the same clock cycle in which ACK* assertion is confirmed. The RD* signal is asserted up until single read operation ends. The BE[3:0]* and address A[31:2] signals remain valid until the clock cycle in which the data is read. The single read cycle ends with the data read clock.

BUSERR* is valid until the clock cycle in which the single read ends (see Figure 4-2).

In the clock cycle in which the TMPR3901F samples BUSERR* to verify that it is asserted, the single read cycle is ended and a Bus Error exception is raised.

SYSCLK

A[31:2]

BE[3:0]*

RD*

BSTART*

LAST*

ACK*

BUSERR*

D[31:0]

Figure 4-2 Bus error during a single read operation

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