Manuals / Toshiba / Computer Equipment / Computer Hardware

Toshiba TX39 user manual Architecture

Models: TX39

1 246

Download 246 pages 24.89 Kb

Page 43

Architecture

(d) BEQL, BNEL, BLEZL, BGTZL, BLTZL, BGEZL, BLTZALL, BGEZALL (ISA Extended Set)

Instruction	Format and Description
Instruction	Format and Description	op	rs		rt	offset


Branch on	BEQL rs, rt, offset
Equal Likely	Branch to the target if the contents of registers rs and rt are equal.
Branch on Not	BNEL rs, rt, offset
Equal Likely	Branch to the target if the contents of registers rs and rt are not equal.
Branch on	BLEZL rs, offset
Less Than or	Branch to the target if register rs is 0 or less.
Equal Zero
Likely
Branch on	BGTZL rs, offset
Greater Than	Branch to the target if register rs is greater than 0.
Zero Likely
Instruction	Format and Description
Instruction	Format and Description	op	rs		funct	offset


Branch on	BLTZL rs, offset
Less Than	Branch to the target if register rs is less than zero
Zero Likely
Branch on	BGEZL rs, offset
Greater Than	Branch to the target if register rs is 0 or greater.
or Equal Zero
Likely
Branch on	BLTZALL rs, offset
Less Than	Store in r31 (link register) the address of the instruction following the instruction
Zero And Link	in the delay slot (the one to be executed during the branch). If register rs is less
Likely	than 0, branch to the target.
Branch on	BGEZALL rs, offset
Greater Than	Store in r31 (link register) the address of the instruction following the instruction
or Equal Zero	in the delay slot (the instruction in the delay slot is executed during the branch).
And Link	If register rs is 0 or greater, branch to the target.
Likely

34

Image 43

Toshiba TX39 user manual Architecture

Contents

TX39 Family Core Architecture Page Toshiba Contents Memory location of exception vectors EPC Exception Program Counter registerCoprocessor Unusable exception Appendix a Instruction Set DetailsBus Interface Unit Bus Controller / Write Buffer 230 227Bus request and bus grant 227 Cache snoop 228 229Architecture Architecture Introduction FeaturesHigh-performance Risc techniques Low power consumption Data notation Signal notationNotation Used in This Manual Mathematical notationArchitecture Overview ArchitectureCPU registers RegistersCP0 registers Exception program counter Reserved †Destination register 5 bits Instruction Set OverviewOperation code 6 bits Source register 5 bitsCoprocessor Load/storeComputational Jump/branchALU Immediate Computational InstructionsALU 3-operand, register type Special Instructions Multiply/DivideJump/Branch Instructions Coprocessor InstructionsCP0 instructions Instruction Description CP0 Instructions Special InstructionBig endian and little endian formats Data Formats and AddressingArchitecture Byte addresses of a misaligned word Pipeline Processing Overview 1 R3900 Processor Core operating modes User modeKernel mode Memory Management Unit MMUKseg1 Direct segment mappingKuseg Kseg0Address mapping Architecture Instruction Formats Instruction Set OverviewInstruction Notation Load and Store Instructions Byte specifications for load and store instructionsBase Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MTHI, Mtlo Instruction Format and Description MFHI, Mflo Instruction Format and DescriptionArchitecture Jump instructions Jump/Branch InstructionsInstruction Format and Description 10. Branch instructions Instruction in the delay slot is executed during the jumpArchitecture 11. Special instructions Special InstructionsCOPz Instruction Format and Description Coprocessor InstructionsBCzT, BCzF Instruction Format and Description Architecture Cache Instruction Format and Description Restore FromSystem Control Coprocessor CP0 Instructions 13. System control coprocessor CP0 instructionsPipeline Architecture Delayed load Delay SlotDelayed branching Nonblocking load function Nonblocking Load FunctionStreaming Divide Instruction DIV, DivuR3900 Processor Core Operating Modes Memory Management Unit MMUInternal MMU virtual address space Direct Segment MappingKuseg 512MB Exception Processing Utlb TLBL2 Cache register Exception Processing RegistersCause register Status registerBits Mnemonic Field name Description Cause register register no.13Read/Write Mnemonic Cause ExcCode fieldRead Status register register no.12Bits Field name DescriptionStatus register 1/2 Bits Mnemonic Field name Description Value on Read IntMask Interrupt Mask KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old NmI Non-maskable InterruptCache register Cache register register no.7DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works PRId Processor Revision Identifier register register no.15 BadVAddr Bad Virtual Address register register no.821-19 Config Configuration register register no.310. Config register2/2 Exception Details ∙ Processing Address Error exception ∙ Causes∙ Exception mask ∙ Applicable instructions∙ Servicing Breakpoint exception ∙ CauseBus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Reserved Instruction exception ∙ Cause Overflow exception ∙ CauseReset exception ∙ Cause Non-maskable interrupt ∙ Cause System Call exception ∙ CauseArchitecture Return from Exception Handler Priority of ExceptionsPriority of Exceptions Exception Mnemonic Architecture Instruction Cache CachesData Cache Data cache configurationLock function Lock bit settingOperation during lock Auto-lock bits Lock bit clearingExample Cache Test FunctionCache disabling Cache flushingCache refill Cache RefillCache Snoop Architecture System Control Processor CP0 Registers Debugging FunctionsDepc †† PRId Processor revision ID Debug †† Debug exception controlDM Debug Mode 0 at reset DBD Debug Branch DelayDebug register register no.16 OES Other Exceptions Status BsF Bus Error Exception FlagSSt Single at reset NIS Non-maskable Interrupt StatusDebug Single Step DSS Debug ExceptionsDSS bit Types of debug exceptionsIi Debug exception handler execution Branching to a debug exception handlerExecuting a Deret instruction Iii Return from a debug exception handlerException priorities Single Step exception ∙ Cause Details of Debug Exceptions∙ Exception masking Debug Breakpoint exception ∙ Cause ∙ Instruction causing this exceptionArchitecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Bitwise logical XOR operation Twos complement divisionExamples of Instruction Notation Function Meaning Table A-2. Common Load/Store FunctionsByte access 8 bits Word access 32 bitsTriplebyte access 24 bits Halfword access 16 bitsJump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Data Bit# Cache NameBit# Cache Operation Description Name CFCz COPz COPzCTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCzMFCz Mfhi Mflo MTC0 MTCz MTCzMthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori Special function OPcodeCOPz rs CP0 Function COPz rtNotation TMPR3901F 200 On-chip peripheral circuits R3900 Processor CoreBus interface for ease of system implementation Package Low power consumption, optimal for portable applicationsDebugging support functions on chip Maximum operating frequencyAddress protection unit Internal BlocksR3900 Processor Core Clock generator Bus interface unit bus controller / write buffer204 R3900 Processor Core ConfigurationInstruction Iimitations Address mapping Clock GeneratorSync NOP Registers Break Address register BAddr0-1 Address Protection UnitBreak Control register BCnt0-1 Break Mask register BMsk0-1Memory protection exception Break Status register BStsBSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 Debug Support UnitSynchronizer Register address mapINT50 INT* signal synchronizationNMI* signal synchronization CPCOND31 CPCOND* signal synchronizationPins Doze signal. Indicates that TMPR3901F is in doze mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Halt signal. Indicates that TMPR3901F is in halt mode∙ Processor Clock OperationsClock ∙ Master ClockSystem clock Master clock ProcessorClock Single Read Read OperationBus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Single write operation 2 waits Write Operation1 NMI InterruptsInterrupt 2 INT50Bus request and bus grant Bus ArbitrationBUSGNT*L Reset Single read operation in half-speed bus mode Half-Speed Bus ModeHalt mode Power-Down Mode232 Standby mode PLL stop Standby ModeDoze Mode Reduced Frequency Mode