Caches, Instruction Cache | Toshiba TX39 instruction

Architecture

Chapter 7 Caches

The R3900 Processor Core is equipped with separate on-chip caches for data and instructions. These caches can be configured in a variety of sizes as required by the user system.

Note : Currently only the cache configuration described below is supported. It consists of a 4 Kbyte instruction cache and 1 Kbyte data cache.

7.1 Instruction Cache

The instruction cache has the following specifications.

− Cache size

: 4 Kbytes (Config register ICS bits = 010)

−Direct mapping

− Block (line) size : 4 words (16 bytes)

−Physical cache

− Burst refill size : Choice of 4/8/16/32 words (set in Config register)

−All valid bits are cleared (made invalid) by a Reset exception

Note : The lock function is not currently supported for the instruction cache. Cache register bits IALc, IALp and IALo do not affect the instruction cache.

Figure 7-1 shows the instruction cache configuration.

World Select : 3

2

1

0

Set address :

20 19

0

31

0 31

0 31

0 31

0

255

V

Physical Tag

Instruction

Instruction

Instruction

Instruction

3

V

Physical Tag

Instruction

Instruction

Instruction

Instruction

2

V

Physical Tag

Instruction

Instruction

Instruction

Instruction

1

V

Physical Tag

Instruction

Instruction

Instruction

Instruction

0

V

Physical Tag

Instruction

Instruction

Instruction

Instruction

V : valid bit (1=valid;0=invalid)

Figure 7-1. Instruction cache configuration

Figure 7-2 shows the instruction cache address field.

31	12 11		4	3	2 1		0
Physical Tag			Cache Tag Index

World Select

Byte Select

Figure 7-2. Instruction cache address field

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Image 86

Toshiba TX39 user manual Caches, Instruction Cache

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 229 227Bus request and bus grant 227 Cache snoop 228 230 Architecture Architecture High-performance Risc techniques FeaturesIntroduction Low power consumption Mathematical notation Signal notationNotation Used in This Manual Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Source register 5 bits Instruction Set OverviewOperation code 6 bits Destination register 5 bits Jump/branch Load/storeComputational Coprocessor ALU 3-operand, register type Computational InstructionsALU Immediate Coprocessor Instructions Multiply/DivideJump/Branch Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview Memory Management Unit MMU User modeKernel mode 1 R3900 Processor Core operating modes Kseg0 Direct segment mappingKuseg Kseg1 Address mapping Architecture Instruction Notation Instruction Set OverviewInstruction Formats Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Instruction Format and Description Jump/Branch InstructionsJump instructions Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions BCzT, BCzF Instruction Format and Description Coprocessor InstructionsCOPz Instruction Format and Description Architecture 13. System control coprocessor CP0 instructions Restore FromSystem Control Coprocessor CP0 Instructions Cache Instruction Format and Description Pipeline Architecture Delayed branching Delay SlotDelayed load Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Status register Exception Processing RegistersCause register Cache register Read/Write Cause register register no.13Bits Mnemonic Field name Description ExcCode field Mnemonic Cause Field name Description Status register register no.12Bits Read Status register 1/2 Bits Mnemonic Field name Description Value on Read NmI Non-maskable Interrupt KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details ∙ Applicable instructions Address Error exception ∙ Causes∙ Exception mask ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Priority of Exceptions Exception Mnemonic Priority of ExceptionsReturn from Exception Handler Architecture Caches Instruction Cache Data cache configuration Data Cache Operation during lock Lock bit settingLock function Lock bit clearing Auto-lock bits Cache flushing Cache Test FunctionCache disabling Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† Debug register register no.16 DBD Debug Branch DelayDM Debug Mode 0 at reset NIS Non-maskable Interrupt Status BsF Bus Error Exception FlagSSt Single at reset OES Other Exceptions Status Types of debug exceptions Debug ExceptionsDSS bit Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Exception priorities Iii Return from a debug exception handlerExecuting a Deret instruction ∙ Exception masking Details of Debug ExceptionsSingle Step exception ∙ Cause ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Halfword access 16 bits Word access 32 bitsTriplebyte access 24 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori COPz rs OPcodeSpecial function COPz rt CP0 Function Notation TMPR3901F 200 Bus interface for ease of system implementation R3900 Processor CoreOn-chip peripheral circuits Maximum operating frequency Low power consumption, optimal for portable applicationsDebugging support functions on chip Package Bus interface unit bus controller / write buffer Internal BlocksR3900 Processor Core Clock generator Address protection unit 204 Instruction Iimitations ConfigurationR3900 Processor Core Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Register address map Debug Support UnitSynchronizer BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Halt signal. Indicates that TMPR3901F is in halt mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Doze signal. Indicates that TMPR3901F is in doze mode ∙ Master Clock OperationsClock ∙ Processor Clock Clock Master clock ProcessorSystem clock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode