TMPR3901F
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2.3 Bus Interface Unit (Bus Controller / Write Buffer)The bus interface unit controls TMPR3901F bus operations. Bus operations are synchronous with the rising
edge of SYSCLK.
The bus interface unit has a four-deep write buffer. The R3900 Processor Core can complete write
operations without pipeline stall.
There may be conflicts between TMPR3901F write requests from the write buffer and read requests by the
R3900 Processor Core. The priority is shown below.
•Write request only :The TMPR3901F issues a write operation to write data from the
write buffer to an external device.
•Read request only : The TMPR3901F issues a read operation to read data from an
external device.
•Both read and write requests : The read operation has priority except in the following cases.
− The data in the write buffer to be written is at the same address as the data to be read.
− Both the data in the write buffer to be written and the data to be read are in uncached areas.
The presence of data in the write buffer can be checked with the BC0T and BC0F instructions.
Data present in write buffer : coprocessor condition is false (0)
Data not present in write buffer : coprocessor condition is true (1)
With this function, processing can wait in loop until the write buffer becomes empty using this function.
An example of this is shown below.
SW
SYNC
NOP
Loop: BC0F Loop
NOP