Div | Toshiba TX39 manual

Architecture

DIV

Divide

DIV

	31	26 25		21 20		16 15			6 5		0
		SPECIAL		rs		rt		0			DIV
		000000						00 0000	0000		011010
		6		5		5		10			6

Format :

DIV rs, rt

Description :

Divides the contents of general register rs by the contents of general register rt, treating both operands as two's complement integers. An overflow exception is never raised. If the divisor is zero, the result is undefined.

Ordinarily, instructions are placed after this instruction to check for zero division and overflow.

The quotient word is loaded into special register LO, and the remainder word into special register HI. When an attempt is made to read the division result using MFHI, MFLO, MADD or MADDU before the divide operation is completed, the read operation is delayed by an interlock.

Divide operations are executed in an independent ALU and can be carried out in parallel with the execution of other instructions. For this reason, the ALU can continue executing instructions even during a cache miss or other delay cycle in which ordinary instructions cannot be processed.

If either of the two preceding instructions is MFHI, MFLO, MADD or MADDU, the results of those instructions are undefined. For the DIV operation to be carried out correctly, reads of HI or LO must be separated from writes by two or more instructions.

Operation :

T − 2: LO ← undefined

HI ← undefined

T − 1: LO ← undefined

HI ← undefined

T:LO ← GPR[rs] div GPR[rt] HI ← GPR[rs] mod GPR[rt]

Exceptions :

None

139

Image 150

Toshiba TX39 user manual Div

Contents

TX39 Family Core Architecture Page Toshiba Contents EPC Exception Program Counter register Memory location of exception vectors Appendix a Instruction Set Details Coprocessor Unusable exception Bus Interface Unit Bus Controller / Write Buffer 229 227Bus request and bus grant 227 Cache snoop 228 230 Architecture Architecture Features IntroductionHigh-performance Risc techniques Low power consumption Mathematical notation Signal notationNotation Used in This Manual Data notation Architecture Architecture Overview Registers CPU registers CP0 registers Reserved † Exception program counter Source register 5 bits Instruction Set OverviewOperation code 6 bits Destination register 5 bits Jump/branch Load/storeComputational Coprocessor Computational Instructions ALU ImmediateALU 3-operand, register type Coprocessor Instructions Multiply/DivideJump/Branch Instructions Special Instructions Special Instruction CP0 instructions Instruction Description CP0 Instructions Data Formats and Addressing Big endian and little endian formats Architecture Byte addresses of a misaligned word Pipeline Processing Overview Memory Management Unit MMU User modeKernel mode 1 R3900 Processor Core operating modes Kseg0 Direct segment mappingKuseg Kseg1 Address mapping Architecture Instruction Set Overview Instruction FormatsInstruction Notation Byte specifications for load and store instructions Load and Store Instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MFHI, Mflo Instruction Format and Description MTHI, Mtlo Instruction Format and Description Architecture Jump/Branch Instructions Jump instructionsInstruction Format and Description Instruction in the delay slot is executed during the jump 10. Branch instructions Architecture Special Instructions 11. Special instructions Coprocessor Instructions COPz Instruction Format and DescriptionBCzT, BCzF Instruction Format and Description Architecture 13. System control coprocessor CP0 instructions Restore FromSystem Control Coprocessor CP0 Instructions Cache Instruction Format and Description Pipeline Architecture Delay Slot Delayed loadDelayed branching Nonblocking Load Function Nonblocking load function Divide Instruction DIV, Divu Streaming Memory Management Unit MMU R3900 Processor Core Operating Modes Direct Segment Mapping Internal MMU virtual address space Kuseg 512MB Exception Processing Utlb TLBL2 Status register Exception Processing RegistersCause register Cache register Cause register register no.13 Bits Mnemonic Field name DescriptionRead/Write ExcCode field Mnemonic Cause Field name Description Status register register no.12Bits Read Status register 1/2 Bits Mnemonic Field name Description Value on Read NmI Non-maskable Interrupt KUc/KUp/KUo Kernel/User mode current/previous/oldIEc/IEp/IEo Interrupt Enable current/previous/old IntMask Interrupt Mask Cache register register no.7 Cache register DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works BadVAddr Bad Virtual Address register register no.8 PRId Processor Revision Identifier register register no.15 Config Configuration register register no.3 21-19 10. Config register2/2 Exception Details ∙ Applicable instructions Address Error exception ∙ Causes∙ Exception mask ∙ Processing Breakpoint exception ∙ Cause ∙ Servicing Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Overflow exception ∙ Cause Reserved Instruction exception ∙ Cause Reset exception ∙ Cause System Call exception ∙ Cause Non-maskable interrupt ∙ Cause Architecture Priority of Exceptions Return from Exception HandlerPriority of Exceptions Exception Mnemonic Architecture Caches Instruction Cache Data cache configuration Data Cache Lock bit setting Lock functionOperation during lock Lock bit clearing Auto-lock bits Cache flushing Cache Test FunctionCache disabling Example Cache Refill Cache refill Cache Snoop Architecture Debugging Functions System Control Processor CP0 Registers PRId Processor revision ID Debug †† Debug exception control Depc †† DBD Debug Branch Delay DM Debug Mode 0 at resetDebug register register no.16 NIS Non-maskable Interrupt Status BsF Bus Error Exception FlagSSt Single at reset OES Other Exceptions Status Types of debug exceptions Debug ExceptionsDSS bit Debug Single Step DSS Branching to a debug exception handler Ii Debug exception handler execution Iii Return from a debug exception handler Executing a Deret instructionException priorities Details of Debug Exceptions Single Step exception ∙ Cause∙ Exception masking ∙ Instruction causing this exception Debug Breakpoint exception ∙ Cause Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Twos complement division Bitwise logical XOR operation Examples of Instruction Notation Table A-2. Common Load/Store Functions Function Meaning Halfword access 16 bits Word access 32 bitsTriplebyte access 24 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Bit# Cache Name Data Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori OPcode Special functionCOPz rs COPz rt CP0 Function Notation TMPR3901F 200 R3900 Processor Core On-chip peripheral circuitsBus interface for ease of system implementation Maximum operating frequency Low power consumption, optimal for portable applicationsDebugging support functions on chip Package Bus interface unit bus controller / write buffer Internal BlocksR3900 Processor Core Clock generator Address protection unit 204 Configuration R3900 Processor CoreInstruction Iimitations Clock Generator Address mapping Sync NOP Address Protection Unit Registers Break Address register BAddr0-1 Break Mask register BMsk0-1 Break Control register BCnt0-1 Break Status register BSts Memory protection exception Register address map Debug Support UnitSynchronizer BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT* signal synchronization INT50 NMI* signal synchronization CPCOND* signal synchronization CPCOND31 Pins Halt signal. Indicates that TMPR3901F is in halt mode Enables internal PLL clockMode quadruple frequency of crystal oscillator Doze signal. Indicates that TMPR3901F is in doze mode ∙ Master Clock OperationsClock ∙ Processor Clock Master clock Processor System clockClock Read Operation Single Read Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Write Operation Single write operation 2 waits Interrupts 1 NMI 2 INT50 Interrupt Bus Arbitration Bus request and bus grant BUSGNT*L Reset Half-Speed Bus Mode Single read operation in half-speed bus mode Power-Down Mode Halt mode 232 Standby Mode Standby mode PLL stop Doze Mode Reduced Frequency Mode