Architecture
26
Table 3-2. Load/store instructions (2/2)
Instruction Format and Description
Store Word SW rt, offset (base)
Generate the address by sign-extending a 32-bit offset and adding it to the
contents of register base. Store the contents of the least significant word of
register rt at the addressed byte.
Store Word
Left SWL rt, offset (base)
Generate the address by sign-extending a 32-bit offset and adding it to the
contents of register base. This instruction is used together with SWR to
store the contents of a register into four consecutive bytes of memory when
the bytes cross a word boundary. The SWL instruction stores the left part of
the register, and SWR stores the right part. SWL shifts the contents of
register rt to the right so that the leftmost byte of the word aligns with the
addressed byte. It then stores the bytes containing the original data in the
corresponding bytes at the addressed byte.
Store Word
Right SWR rt, offset (base)
Generate the address by sign-extending a 32-bit offset and adding it to the
contents of register base. SWR shifts the contents of register rt to the left so
that the rightmost byte of the word aligns with the addressed byte. It then
stores the bytes containing the original data in the corresponding bytes at the
addressed byte.
Table 3-3. Load/store instructions (R3000A extended set)
Instruction Format and Description
SYNC SYNC Interlock the pipeline while a load or store instruction is executing, until
execution is completed.
offset
funct
rtbase
0
op
op