Architecture

6.3.5Coprocessor Unusable exception

Cause

Attempting to execute a coprocessor CPz instruction when its corresponding CUz bit in the Status register is cleared to 0 (coprocessor unusable).

In user mode, attempting to execute a CP0 instruction when the CU0 bit is cleared to 0. (In kernel mode, an exception is not raised when a CP0 instruction is issued, regardless of the CU0 bit setting.)

Exception mask

The Coprocessor Unusable exception is not maskable.

Applicable instructions

Coprocessor instructions : LWCz, SWCz, MTCz, MFCz, CTCz, CFCz, COPz, BCzT, BCzF, BCzTL, BCzFL

Coprocessor 0 instructions : MTC0, MFC0, RFE, COP0

Processing

The common exception vector (0x8000 0080) is used.

CpU(11) is set for ExcCode in the Cause register.

The coprocessor number referred to at the time of the exception is stored in the Cause register CE (Coprocessor Error) field.

The EPC register points to the address of the instruction causing the exception. If, however, that instruction is in the branch delay slot (for execution during a branch), the immediately preceding branch instruction address is retained in the EPC register and the Cause register BD bit is set to 1.

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Toshiba TX39 user manual Coprocessor Unusable exception ∙ Cause