Toshiba TX39 user manual Status register register no.12, Bits, Field name Description, Read, Write

Models: TX39

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Architecture

6.2.3Status register (register no.12)

This register holds the operating mode status (user mode or kernel mode), interrupt masking status, diagnosis status and similar information.

31

28

 

 

25

 

 

 

22

21

 

20

19 16 15

 

8

76

5

 

4

 

3

2

1

 

0

 

CU[3:0]

0

RE

 

0

 

BEV

T

 

Nml

0

 

 

IntMask

 

0

KUo

 

IEo

 

KUp

 

IEp

KUc

 

IEc

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

Int[5:0] Sw[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

2

1

 

2

 

1

1

 

1

4

 

 

8

 

2

1

 

1

 

1

1

1

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

Mnemonic

Field name

 

 

Description

 

 

 

 

Value on

 

Read/

 

 

 

 

 

 

 

 

 

 

Reset

 

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31-28

 

 

CU

 

 

Coprocessor

 

The usability of the four coprocessors

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

Usability

 

 

CP0 through CP3 is controlled by bits

 

 

 

 

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CU0 to CU3, with 1 = usable and 0 =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

unusable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

RE

 

 

Reverse

 

 

Setting this bit in user mode reverses the

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

Endian

 

 

 

initial setting of the endian.

 

 

 

 

 

 

 

 

Write

 

 

 

22

 

 

BEV

 

 

Bootstrap

 

 

When this bit is set to 1, if a UTLB Refill

1

 

 

 

Read/

 

 

 

 

 

 

 

 

 

Exception

 

 

exception or general exception occurs,

 

 

 

 

Write

 

 

 

 

 

 

 

 

 

 

Vector

 

 

 

the alternate bootstrap vector (the vector

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

address shown in parentheses in Table

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6-2) is used.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

TS

 

 

TLB Shutdown

 

This bit is set to 1 when the TLB

 

 

1

 

 

 

Read

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

becomes unusable. It is always set to 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when the internal MMU is enabled.

 

 

 

 

 

 

 

 

 

 

 

20

 

 

NmI

 

 

Non-maskable

 

This bit is set to 1 when a non-maskable

0

 

 

 

Read/

 

 

 

 

 

 

 

 

 

Interrupt

 

 

interrupt occurs.

Writing 1 to this bit

 

 

 

 

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clears it to 0.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15-8

 

 

IntMask

Interrupt Mask

 

These are mask bits corresponding to

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

hardware interrupts Int5..0 and software

 

 

 

 

Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

interrupts Sw1..0.

Here 1 = interrupt

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

enabled and 0 = interrupt masked.

 

 

 

 

 

 

 

 

 

 

 

5

 

 

KUo

 

 

Kernel/User

 

0

= kernel mode;

 

 

 

 

 

 

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

Mode old

 

 

1

= user mode.

 

 

 

 

 

 

 

 

 

 

Write

 

 

 

4

 

 

IEo

 

 

Interrupt

 

 

1

= interrupt enabled;

 

 

 

 

 

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

Enabled old

 

0

= interrupt masked.

 

 

 

 

 

 

 

 

 

Write

 

 

 

3

 

 

KUp

 

 

Kernel/User

 

0

= kernel mode;

 

 

 

 

 

 

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

Mode previous

 

1

= user mode.

 

 

 

 

 

 

 

 

 

 

Write

 

 

 

2

 

 

IEp

 

 

Interrupt

 

 

1

= interrupt enabled;

 

 

 

 

 

Undefined

 

Read/

 

 

 

 

 

 

 

 

 

Enabled

 

 

0

= interrupt masked.

 

 

 

 

 

 

 

 

 

Write

 

 

 

 

 

 

 

 

 

 

previous

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

KUc

 

 

Kernel/User

 

0

= kernel mode;

 

 

 

 

 

 

0

 

 

 

Read/

 

 

 

 

 

 

 

 

 

Mode current

 

1

= user mode.

 

 

 

 

 

 

 

 

 

 

Write

 

 

 

0

 

 

IEc

 

 

Interrupt

 

 

1

= interrupt enabled;

 

 

 

 

 

0

 

 

 

Read/

 

 

 

 

 

 

 

 

 

Enabled

 

 

0

= interrupt masked.

 

 

 

 

 

 

 

 

 

Write

 

 

 

 

 

 

 

 

 

 

current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Used mainly for diagnosis and testing.

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Page 62
Image 62
Toshiba TX39 user manual Status register register no.12, Bits, Field name Description, Read, Write