Load and Store Instructions | Toshiba TX39 specs

Architecture

3.3 Load and Store Instructions

Load and Store instructions move data between memory and general registers and are all I-type instructions. The only directly supported addressing mode is base register plus 16-bit signed immediate offset.

With the R3900 Processor Core, the result of a load instruction can be used by the immediately following instruction. Execution of the following instruction is delayed by hardware interlock until the load result becomes available. The instruction position immediately following the load instruction is referred to as the load delay slot . In the case of the LWL (Load Word Left) and LWR (Load Word Right) instructions, however, it is possible to use the destination register of an immediately preceding load instruction as the target register of the LWL or LWR instruction.

The access type, which indicates the size of data to be loaded or stored, is determined by the operation code (op) of the load or store instruction. The target address of a load or store is always the smallest byte address of the target data byte string, regardless of the access type or endian. This address is the most significant byte for the big endian format, and the least significant byte for the little endian format.

The position of the accessed data is determined by the access type and the two low-order address bits, as shown in Table 3-1.

Designating a combination other than those shown in table 3-1 results in an Address Error exception.

Table 3-1. Byte specifications for load and store instructions

	Low order								Accessed Bytes

Access Type	address bits					Big Endian								Little Endian
	1	0	31						0		31						0
	1	0	31						0		31						0


word	0	0		0		1	2		3			3		2	1		0

triple-byte	0	0		0		1	2							2	1		0


	0	1				1	2		3			3		2	1


halfword	0	0		0		1									1		0

	1	0					2		3			3		2
	1	0


	0	0		0													0


byte	0	1				1									1


	1	0					2							2


	1	1							3			3

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Toshiba TX39 user manual Load and Store Instructions, Byte specifications for load and store instructions

Contents

TX39 Family Core Architecture Page Toshiba Contents Memory location of exception vectors EPC Exception Program Counter register Coprocessor Unusable exception Appendix a Instruction Set Details Bus Interface Unit Bus Controller / Write Buffer Bus request and bus grant 227 Cache snoop 228 227229 230 Architecture Architecture Features IntroductionHigh-performance Risc techniques Low power consumption Notation Used in This Manual Signal notationMathematical notation Data notation Architecture Overview Architecture CPU registers Registers CP0 registers Exception program counter Reserved † Operation code 6 bits Instruction Set OverviewSource register 5 bits Destination register 5 bits Computational Load/storeJump/branch Coprocessor Computational Instructions ALU ImmediateALU 3-operand, register type Jump/Branch Instructions Multiply/DivideCoprocessor Instructions Special Instructions CP0 instructions Instruction Description CP0 Instructions Special Instruction Big endian and little endian formats Data Formats and Addressing Architecture Byte addresses of a misaligned word Pipeline Processing Overview Kernel mode User modeMemory Management Unit MMU 1 R3900 Processor Core operating modes Kuseg Direct segment mappingKseg0 Kseg1 Address mapping Architecture Instruction Set Overview Instruction FormatsInstruction Notation Load and Store Instructions Byte specifications for load and store instructions Base Offset Sync Computational Instructions NOR SLLV, SRLV, Srav Instruction Format and Description MTHI, Mtlo Instruction Format and Description MFHI, Mflo Instruction Format and Description Architecture Jump/Branch Instructions Jump instructionsInstruction Format and Description 10. Branch instructions Instruction in the delay slot is executed during the jump Architecture 11. Special instructions Special Instructions Coprocessor Instructions COPz Instruction Format and DescriptionBCzT, BCzF Instruction Format and Description Architecture System Control Coprocessor CP0 Instructions Restore From13. System control coprocessor CP0 instructions Cache Instruction Format and Description Pipeline Architecture Delay Slot Delayed loadDelayed branching Nonblocking load function Nonblocking Load Function Streaming Divide Instruction DIV, Divu R3900 Processor Core Operating Modes Memory Management Unit MMU Internal MMU virtual address space Direct Segment Mapping Kuseg 512MB Exception Processing Utlb TLBL2 Cause register Exception Processing RegistersStatus register Cache register Cause register register no.13 Bits Mnemonic Field name DescriptionRead/Write Mnemonic Cause ExcCode field Bits Status register register no.12Field name Description Read Status register 1/2 Bits Mnemonic Field name Description Value on Read IEc/IEp/IEo Interrupt Enable current/previous/old KUc/KUp/KUo Kernel/User mode current/previous/oldNmI Non-maskable Interrupt IntMask Interrupt Mask Cache register Cache register register no.7 DALc/DALp/DALo Data Cache Auto-Lock current/previous/old IAL DAL Shows how the RFE instruction works PRId Processor Revision Identifier register register no.15 BadVAddr Bad Virtual Address register register no.8 21-19 Config Configuration register register no.3 10. Config register2/2 Exception Details ∙ Exception mask Address Error exception ∙ Causes∙ Applicable instructions ∙ Processing ∙ Servicing Breakpoint exception ∙ Cause Bus Error exception ∙ Causes Architecture Coprocessor Unusable exception ∙ Cause Interrupts ∙ Cause Reserved Instruction exception ∙ Cause Overflow exception ∙ Cause Reset exception ∙ Cause Non-maskable interrupt ∙ Cause System Call exception ∙ Cause Architecture Priority of Exceptions Return from Exception HandlerPriority of Exceptions Exception Mnemonic Architecture Instruction Cache Caches Data Cache Data cache configuration Lock bit setting Lock functionOperation during lock Auto-lock bits Lock bit clearing Cache disabling Cache Test FunctionCache flushing Example Cache refill Cache Refill Cache Snoop Architecture System Control Processor CP0 Registers Debugging Functions Depc †† PRId Processor revision ID Debug †† Debug exception control DBD Debug Branch Delay DM Debug Mode 0 at resetDebug register register no.16 SSt Single at reset BsF Bus Error Exception FlagNIS Non-maskable Interrupt Status OES Other Exceptions Status DSS bit Debug ExceptionsTypes of debug exceptions Debug Single Step DSS Ii Debug exception handler execution Branching to a debug exception handler Iii Return from a debug exception handler Executing a Deret instructionException priorities Details of Debug Exceptions Single Step exception ∙ Cause∙ Exception masking Debug Breakpoint exception ∙ Cause ∙ Instruction causing this exception Architecture Appendix a Instruction Set Details Instruction Classes Instruction Formats Instruction Notation Conventions Bitwise logical XOR operation Twos complement division Examples of Instruction Notation Function Meaning Table A-2. Common Load/Store Functions Triplebyte access 24 bits Word access 32 bitsHalfword access 16 bits Byte access 8 bits Jump and Branch Instructions ADD Addi Addiu Addu Rd, rs, rt Andi BCzF Operation Code Bit Encoding BCzFL 111 BCzT 113 BCzTL 115 BEQ Beql Bgez Bgezal Bgezall Bgezl Bgtz Bgtzl Blez Blezl Bltz Bltzal Bltzall Bltzl BNE Bnel Break Data Bit# Cache Name Bit# Cache Operation Description Name CFCz COPz COPz CTCz Deret DIV Divu Jump JAL Jalr JR rs LB rt, offsetbase LBU LH rt, offsetbase LHU LUI LW rt, offsetbase LWL 152 LWR 154 Multiply/Add Maddu MFC0 MFCz MFCz MFCz Mfhi Mflo MTC0 MTCz MTCz Mthi Mtlo Mult Multu NOR Or rd, rs, rt ORI RFE SB rt, offsetbase Sdbbp SH rt, offsetbase SLL Sllv SLT Slti Sltiu Sltu SRA Srav SRL Srlv SUB Subu SW rt, offsetbase SWL 189 SWR 191 Sync Syscall XOR Xori OPcode Special functionCOPz rs CP0 Function COPz rt Notation TMPR3901F 200 R3900 Processor Core On-chip peripheral circuitsBus interface for ease of system implementation Debugging support functions on chip Low power consumption, optimal for portable applicationsMaximum operating frequency Package R3900 Processor Core Clock generator Internal BlocksBus interface unit bus controller / write buffer Address protection unit 204 Configuration R3900 Processor CoreInstruction Iimitations Address mapping Clock Generator Sync NOP Registers Break Address register BAddr0-1 Address Protection Unit Break Control register BCnt0-1 Break Mask register BMsk0-1 Memory protection exception Break Status register BSts Synchronizer Debug Support UnitRegister address map BSts 0xFF00 BAddr0 Bcnt0 BMsk0 BAddr1 Bcnt1 BMsk1 INT50 INT* signal synchronization NMI* signal synchronization CPCOND31 CPCOND* signal synchronization Pins Mode quadruple frequency of crystal oscillator Enables internal PLL clockHalt signal. Indicates that TMPR3901F is in halt mode Doze signal. Indicates that TMPR3901F is in doze mode Clock Operations∙ Master Clock ∙ Processor Clock Master clock Processor System clockClock Single Read Read Operation Bus error during a single read operation Burst Read Burst read 4 words 1 wait Bus error in burst read operation 4 words Single write operation 2 waits Write Operation 1 NMI Interrupts Interrupt 2 INT50 Bus request and bus grant Bus Arbitration BUSGNT*L Reset Single read operation in half-speed bus mode Half-Speed Bus Mode Halt mode Power-Down Mode 232 Standby mode PLL stop Standby Mode Doze Mode Reduced Frequency Mode