Cypress SL811HS Ordering Information

SL811HS

Document 38-08008 Rev. *D Page 30 of 32

Clock Timing Specifications

Ordering Information

CLK

CLOCK TIMING

trisetfallthigh

tclk tlow

Clock Timing

Parameter Description Min. Typ. Max.

tCLK Clock Period (48 MHz) 20.0 ns 20.8 ns

tHIGH Clock HIGH Time 9 ns 11 ns

tLOW Clock LOW Time 9 ns 11 ns

tRISE Clock Rise Time 5.0 ns

tFALL Clock Fall Time 5.0 ns

Clock Duty Cycle 45% 55%

Part Number Package Type

SL811HS 28-pin PLCC –

SL811HS-JCT 28-pin Lead free –

SL811HST-AXC 48-pin Lead free –

Package Diagrams

DIMENSIONSIN INCHES MIN.

MAX.

0.045

0.055

0.026

0.013

0.032

0.021

0.020MIN.

0.090

0.165

0.120

0.180

0.485

0.495

0.450

0.458

0.450

0.495

0.485

0.390

0.430

426

1812

0.004

SEATINGPLANE

PIN#1ID

28-Lead Plastic Leaded Chip Carrier J64

51-85001-*A

Contents

Main SL811HS Embedded USB Host/Slave Controller SL811HS Features Block Diagram Introduction Page SL811HS Registers Page Page Page Page Page Page Page SL811HS Page Page Page Page Page Page Document 38-08008 Rev. *D Page 18 of 32 Physical Connections Figure 4. 28-pin PLCC USB Host/Slave Controller Pin Layout 28 PLCC 28-Pin PLCC Mechanical Dimensions Page Document 38-08008 Rev. *D Page 20 of 32 48-Pin TQFP Physical Connections 48-Pin TQFP AXC Pin Layout NC 12 48-Pin TQFP Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout Page Page Page Electrical Specifications Page nWR A0 D0-D7 DATA nCS I/O Write Cycle to R e g is te r o r Memory Buffer nRD A0 D0-D7 DATA nCS I/O Read Cycle from Register or Mem o ry Buffer nWR DMA Write Cycle nDRQ nDACK D0-D7 DATA nRD SL811 DMA READ C YC LE TIMING nRST SL811 DMA Read Cycle Timing treset nRD or nWR Reset Timing Ordering Information CLK CLOCK TIMING Package Diagrams Document History Page