Ordering Information, Package Diagrams

SL811HS

Clock Timing Specifications

tclk

CLK

thigh

tlow

tfall

trise

CLOCKClock TimingTIMING

Parameter	Description	Min.	Typ.	Max.

tCLK	Clock Period (48 MHz)	20.0 ns	20.8 ns
tHIGH	Clock HIGH Time	9 ns		11 ns
tLOW	Clock LOW Time	9 ns		11 ns
tRISE	Clock Rise Time			5.0 ns
tFALL	Clock Fall Time			5.0 ns
	Clock Duty Cycle	45%		55%

Ordering Information

Part Number		Package Type
SL811HS	28-pin PLCC		–

SL811HS-JCT	28-pin Lead free		–

SL811HST-AXC	48-pin Lead free		–

Package Diagrams

28-Lead Plastic Leaded Chip Carrier J64

PIN #1 ID

0.450

0.485 0.458

0.495

126

0.450

0.458

0.485

0.495

SEATING PLANE

0.045

0.055

0.026

0.032

DIMENSIONS IN INCHES MIN.

MAX.

0.004

0.013

0.021

0.390

0.430

0.020 MIN.

0.090

0.120

0.165		51-85001-*A
0.180

Document 38-08008 Rev. *D

Page 30 of 32

Page 30

Image 30

Cypress SL811HS manual Ordering Information, Package Diagrams, CLOCKClock TimingTIMING Parameter Description Min Typ Max

Contents

Master/Slave Controller FeaturesIntroduction Cypress Semiconductor Corporation Data Port, Microprocessor Interface DMA Controller slave mode onlyAuto Address Increment Mode Interrupt Controller Frequency Tolerance SL811HS RegistersMHz Crystals USB Transceiver Register Values on Power Up and Reset USB Control RegistersSL811HS Host Control Registers ISO Bit Position Bit Name FunctionHBADD5 HBADD4 HBADD3 HBADD2 HBADD1 HBADD0 PID Type HBL7 HBL6HBL4 HBL3 HBL2 HBL1 HBL0 D7-D4 DA6 DA5 DA4 DA3 DA2 DA1 DA0 HTC7HTC2 DA7 Control Register 1 Address 05h Bit Low-power Modes Bit 6 Control Register, Address 05hUSB Reset Sequence Control Register 1 Address 05h Bits 3 Done Interrupt Enable Register Address 06hUSB-B USB-A USB-B Done USB-B Interrupt Status Register Address 0Dh BitValue of the Data+ pin Revision Reserved Bit Position Bit Name Function SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0 Endpoints 0-3 Register Addresses Register Name Miscellaneous register addressesEndpoint Registers Endpoints 0-3 Register Addresses Next Data Set Endpoint Control RegistersSequence EPxLEN1 EPxLEN0 Current Data Set Register Reserved OverflowTransmission Acknowledge Control Register 0Fh SOF Low Byte Register Control Register 1 Address 05h Stbyd SpselStbyd USBADD5 USBADD4 USBADD3 USBADD2 USBADD1 USBADD0 USB Address Register, Address 07h. This registerUSB Address Register Address 07h Interrupt Status Register Address 0Dh Reserved Master/Slave Current Data Set Register Address 0EhControl Register 2 Address 0Fh Bit SL811HS Pin Plcc Physical Connections Pin Plcc Mechanical DimensionsPhysical Connections Pin Plcc Pin Layout Diagram below illustrates a simple +3.3V voltage source Package Markings 28-pin Plcc Pin Tqfp Physical Connections Pin Tqfp AXC Pin Layout 48/28-Pin USB Host Controller Pins Description Power for USB Transceivers . V DD1 may be connected to V DD Data 7. Microprocessor Data/Address Bus Master/Slave Mode Select. ’1’ selects Slave. ’0’ = MasterData 6. Microprocessor Data/Address Bus Buffer or register Yyww Xxxx Package Markings 48-Pin Tqfp Electrical Specifications DC Characteristics Parameter Description Min Typ Max Parameter Description Min Typ Max Bus Interface Timing RequirementsWrite Cycle NWR High Read Cycle DMA Write Cycle DMA Write Cycle NRst Pulse width Reset TimingDMA Read Cycle NRst High to nRD or nWR active CLOCKClock TimingTIMING Parameter Description Min Typ Max Package DiagramsOrdering Information Part Number Package Type Lead Thin Plastic Quad Flat Pack 7x7x1.4 mm A48 Issue Date Orig. Description of Change Document HistoryREV ECN no

Cypress SL811HS manual Ordering Information, Package Diagrams, Part Number Package Type

Models: SL811HS

CLK

CLOCKClock TimingTIMING

Parameter

Description

Min.

Typ.

Max.

Ordering Information

Part Number

Package Type

SL811HS

Package Diagrams

28-Lead Plastic Leaded Chip Carrier J64