Yamaha YMF724F DPLL1 Disable PLL1 Clock Oscillation, PSL0 Power Save Legacy Audio Block, B10, B11

YMF724F

b2	................DPLL1: Disable PLL1 Clock Oscillation
	Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function.
	“0”: Normal	(default)
	“1”: Disable
b3	................PSL0: Power Save Legacy Audio Block 0
	Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0. This block
	includes OPL3 and SB Pro engines.
	“0”: Normal	(default)
	“1”: Power Save
b4	................PSL1: Power Save Legacy Audio Block 1
	Setting this bit to “1” stops providing the clock with the Legacy Audio function block 1. This block
	includes MPU401 and Joystick.
	“0”: Normal	(default)
	“1”: Power Save
b5	................PSN: Power Save PCI Audio block
	Setting this bit to “1” stops providing the clock with the PCI Audio function block. This block includes
	PCI Audio, SRC, AC3F2 I/F, AC-2 I/F, H/W Vol. and SPDIF.
	“0”: Normal	(default)
	“1”: Power Save
b8	................PR0: AC-2 Power down Control 0

This bit controls the power state of the ADC and Input Mux in AC-2.

	“0”: Normal	(default)
	“1”: Power down
b9	................PR1: AC-2 Power down Control 1

This bit controls the power state of the DAC in AC-2.

	“0”: Normal	(default)
	“1”: Power down
b10	..............PR2: AC-2 Power down Control 2

This bit controls the power state of the Analog Mixer (Vref still on) in AC-2. This power state retains

the Reference Voltage of AC-2.

	“0”: Normal	(default)
	“1”: Power down
b11	..............PR3: AC-2 Power down Control 3

This bit controls the power state of the Analog Mixer (Vref off) in AC-2. This power state removes

Reference Voltage of AC-2.

“0”: Normal (default)

“1”: Power down

September 21, 1998

-22-