Intel SE7221BK1-E manual ICH6 Ioapic DMI Interface, Gmch Intr CPU

Page 32

IRQ0

IRQ1

IRQ2

IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ8

IRQ9

IRQ10

IRQ11

IRQ12

IRQ13

IRQ14

IRQ15

IRQ16

IRQ17

IRQ18

IRQ19

IRQ20

IRQ21

IRQ22

IRQ23

ICH6

SE7221BK1-ETechnical Product Specification

ICH6 IOAPIC 0

DMI INTERFACE

ICH6

8259PIC

X8

connector

X8 PCI-E interface

GMCH

INTR

CPU

Figure 3. Interrupt Routing Diagram

20

Revision 1.3

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Contents Intel Server Board SE7221BK1-E Date Revision Modifications Number SE7221BK1-ETechnical Product SpecificationRevision SE7221BK1-E Technical Product Specification DisclaimersTable of contents Connectors Configuration JumpersBios Setup Utility Acpi ImplementationSE7221BK1 -E Technical Product Specification Boot Block Post Progress Codes Power InformationAbsolute Maximum Ratings Hardware MonitoringIndustry Canada ICES-003 GlossaryList of Tables ViiiSE7221BK1-E Technical Product Specification Revision List of Figures Page Introduction SE7221BK1-E Feature Set Server Board Overviewƒ USB ƒ LPC Low Pin Count bus segment with one embedded devicesCPU PCI-X 100 SlotFunctional Architecture Processor SubsystemMemory Subsystem Interrupts and ApicMemory Dimm Support Processor Support MatrixMemory Configuration Location Dimm Label Channel Population Order Memory Bank Label DefinitionThroughput Level Configuration Characteristics Intel E7221 Chipset1.1 DDR2 Configurations Gmch Memory Architecture OverviewGraphics Memory Controller Hub Gmch Supported DDR2 modules3 ICH6R PCI Bus P32-A I/O SubsystemPower Management PCI Express* X4 SubsystemPCI Bus Master IDE Interface USB InterfaceSuper I/O Serial PortsBios Flash O SubsystemPCI Subsystem System Health Support2.2 P32-B Arbitration 2 P32-B 66-MHz PCI-X Subsystem SE7221BK1LX sku only1.2 P32-A Arbitration P64-C Configuration IDs 3 P64-C 66/100-MHz PCI-X Subsystem3.2 P64-C Arbitration P32-B Arbitration ConnectionsNIC Connector and Status LEDs Video ControllerNetwork Interface Controller NIC PCI-EInterrupt Routing Legacy Interrupt RoutingApic Interrupt Routing Legacy Interrupt SourcesISA Interrupt Description PCI Error HandlingSerialized IRQ Support Gmch Intr CPU ICH6ICH6 Ioapic DMI Interface Super I/O PCI InterfacePA IRQ8 Interface PB IRQ8 InterfaceAcpi Front Panel SwitchesAcpi Implementation Power Button On to Off Legacy Power Button On to Off Acpi Wake up Sources Acpi and LegacySupported Wake Events USBConnectors Main Power ConnectorPower Connector Pin-out CN4H1 Auxiliary CPU Power Connector Pin-out CN4B1Front Panel Connector I2C HeaderHsbp Header Pin-out J1D1 LCD Header Pin-out J1C1VGA Connector NIC ConnectorVGA Connector Pin-out J8A1 NIC1-82541PI10/100/1000 Connector Pin-out J5A1IDE Connector NIC2-82541PI 10/100/1000 Connector Pin-out J6A1ATA 40-pin Connector Pin-out J3J1 IDEA1 Diag IDEA0 IDEA2 IDEDCS0# IDEDCS1# IDEHDACT# GNDSata Connector USB ConnectorSata Connector Pin-out J1G1, J1G2, J1J2, J2J1 USB Connectors Pin-out J5A1Floppy Connector Serial Port ConnectorLegacy 34-pin Floppy Connector Pin-out JP3J1 External DB9 Serial a Port Pin-out J8A1Keyboard and Mouse Connector Keyboard and Mouse PS/2 Connectors Pin-out KM9A1Miscellaneous Headers Fan HeaderIntrusion Cable Connector Intrusion Cable Connector J1A1Pin-Out Pin Signal NameHDD LED Header J1E1 Pin-Out Pin Signal Name HDD LED HeaderConfiguration Jumpers System Recovery and Update JumpersRolling Bios selection header System Recovery and Update Jumper OptionsBios Setup Utility Configuration ResetKeyboard Commands LocalizationLoad Setup Defaults? CancelESC PostEntering Bios Setup Bios Setup, Main Menu OptionsSave configuration changes and exit setup? Feature Options Help Text DescriptionProcessor configuration sub-menu Bios Setup, Advanced Menu OptionsBios Setup, Processor configuration sub-menu options Advanced menuIDE configuration sub-menu Bios Setup IDE Configuration Menu OptionsEnabled CompatibleBios Setup, IDE Device Configuration Sub-menu Selections Host & DeviceAuto Cdrom ArmdFloppy configuration sub-menu Super I/O configuration sub-menuBios Setup, Floppy Configuration Sub-menu Selections Bios Setup, Super I/O Configuration Sub-menuUSB configuration sub-menu Bios Setup, USB Configuration Sub-menu SelectionsPCI configuration sub-menu Bios Setup, PCI Configuration Sub-menu SelectionsFDD CdromBoot menu Memory configuration sub-menuBios Setup, Memory Configuration Sub-menu Selections Bios Setup, Boot Menu SelectionsBoot settings configuration sub-menu selections Boot device priority sub-menu selectionsBios Setup, Boot Settings Configuration Sub-menu Selections Bios Setup, Boot Device Priority Sub-menu SelectionsNorth Bridge Chipset Configuration Bios Setup, Removable Drives Sub-menu SelectionsBios Setup, Atapi Cdrom Drives Sub-menu Selections Chipset MenuSouth Bridge Chipset Configuration Enabled, 8MBFeature Options Help Text Dram ClocksSecurity menu PXH Bridge ConfigurationBios Setup, Security Menu Options Minute Bios Setup, Server Menu SelectionsServer menu Bios Setup, System Management Sub-menu Selections System management sub-menu selectionsStays Off Stay OnSerial Console features sub-menu selections Event Log configuration sub-menu selectionsBios Setup Serial Console Features Sub-menu Selections Bios Setup, Event Log Configuration Sub-menu SelectionsUpgrading the Bios Preparing for the UpgradeRecording the Current Bios Settings Bios Setup, Exit Menu SelectionsObtaining the Upgrade Utility Creating a Bootable Diskette Flash Update UtilityFlash Architecture and Flash Update Utility Rolling Bios and On-line updatesRecovery Mode Bios RecoveryMulti-Disk Recovery \split AMIBOOT.ROM AmibootManually Recovering the Bios Summary of Beep codesError Handling and Reporting Post Error Beep CodesPost Error Beep Codes Beeps Error Message Post Progress Code DescriptionBios Event Log Post Error Messages and HandlingError Code Error Message Response PmmmemallocerrPost Progress Codes and Messages Post Code CheckpointsPost Code Checkpoints LanguagemoduleerrEnable IRQ-0 in PIC for system timer interrupt Initializes remaining option ROMs Boot Block Initialization Code Checkpoints Bootblock Initialization Code CheckpointsBoot Block Recovery Code Checkpoints Bootblock Recovery Code CheckpointsDIM Code Checkpoints Acpi Runtime CheckpointsDIM Code Checkpoints Acpi Runtime CheckpointsDiagnostic LEDs Diagnostic LED Post Progress CodesBoot Block Post Progress Codes Post Progress Code LED ExamplePost Progress Codes SE7221BK1-ETechnical Product Specification SE7221BK1-E Technical Product Specification Power Information Intel Server Board SE7221BK1-E Power BudgetBoard Power Budget Power Supply Rail Voltages Units WattsPower Supply Specifications Power Timing RequirementsBoard Power Supply Voltage Specification 5VSB output voltage rise time shall be from 1.0ms to 25.0msOutput Voltage Timing Turn On/Off Timing +5VSB Dynamic LoadingTransient Load Requirements AC Line Transient Specification AC Line Fast Transient EFT SpecificationAbsolute Maximum Ratings AC Line Sag Transient PerformanceHardware Monitoring Mean Time Between Failures Mtbf Test ResultsMonitored Components Monitored ComponentsHTHEMPDA/C TemperatureFANIN7 PIN #9 Fan Speed Control Block Diagram Fan Speed ControlProduct Safety Compliance Product Regulatory ComplianceChassis Intrusion Product EMC ComplianceElectromagnetic Compatibility Notices FCC USAKorean RRL Compliance Europe CE Declaration of ConformityTaiwan Declaration of Conformity Replacing the Back-Up Battery Australia / New ZealandMechanical Specifications Product Code Calculated Mtbf Operating TemperatureCalculated Mean Time Between Failures Mtbf Mtbf DataSE7221BK1-E Server Board Mechanical Drawing Sku 1 Pedestal mount I/O shield mechanical drawing Revision Sku 2 Pedestal mount I/O shield mechanical drawing Page Glossary SE7221BK1-E Technical Product Specification Term DefinitionLPC MBEMSB MtbfSE7221BK1-E Technical Product Specification Glossary VGAVID ZCR
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