Intel Dual-Core Intel Xeon processor LV, Intel E7520 MCH and Intel 6300ESB ICH Chipset

Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH

3.3.1Dual-Core Intel® Xeon® processor LV

•667 MHz FSB

3.3.2Intel® E7520 MCH and Intel® 6300ESB ICH Chipset

The features of the chipsets are detailed below.

3.3.2.1Intel® E7520 MCH Memory Controller Hub (MCH)

The architecture of the MCH provides the performance and feature set required for dual processor-based volume to performance servers. Configuration options facilitate optimization of the platform for workloads characteristic of communication, presentation, storage, performance computation, or database applications. Coverage includes the MCH interface units (system bus, system memory, PCI Express, Hub Interface (HI), SMBus, power management, MCH clocking, MCH system reset and power sequencing) as well as RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features.

Features:

•Registered ECC DIMM support

•Integrated four-channel DMA engine with IOxAPIC functionality

•High speed serial PCI Express interface

•Hub interface to 6300ESB ICH

3.3.2.2Intel® 6300ESB I/O Controller Hub (ICH)

The Intel® 6300ESB ICH is designed for a variety of processors/memory controller hubs. The 6300ESB provides the data buffering and interface arbitration required to ensure that system interfaces operate efficiently and provide the bandwidth necessary to enable the system to obtain peak performance.

Features:

•Upstream HI for access to the MCH

•Two port Serial ATA controllers

•IDE connector

•PCI-X 1.0 Interface

•PCI 2.2 Interface

•Two serial I/O ports

•Two-stage WDT (Watch Dog Timer)

•LPC Interface

•EPLD for Port 80 decode and display

•FWH Interface

•SMBus 2.0 controller

•I/O APIC

•Four USB 2.0 Ports

	Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH
April 2007	User’s Manual
Order Number: 311274-009	27