Intel E7520 user manual VRD VID Headers, IRQ Routing Diagram

Dual-Core Intel Xeon processor LV / E7520 Chipset / 6300ESB ICH

Figure 20. IRQ Routing Diagram

	MSI
CPU0	NMI
	SMI	FSB
	SMI	NMI

FSB

MCH

	MSI
PCI-E	MSI MSI

PCI-E	PCI-E	PCI-E
8x	8x	8x
MSI	MSI	MSI
PCI-E	PCI-E	PCI-E

	MSI
CPU0	NMI
	SMI

HI	MSI
		HI

	IDE
MSI	IRQ14/15	PIRQ	A	PCI32/33
			E
			B
			C
			D
			F
NMI	ICH
			G
			H

	PXIRQ	A	PCI-X64/66
		B
		C
SERIRQ		D
SMI

PCI Slot	Video
REQ/GNT: 0	REQ/GNT: 1
IDSEL: AD16	IDSEL: AD17
A B C D	A

PCI-X Slot

REQ/GNT: 0

IDSEL: AD17

A B C D

PCI-X Slot

REQ/GNT: 1

IDSEL: AD18

A B C D

SIO

3.3.14VRD VID Headers

VID headers provide for manual control of the processor core voltage regulator output level(s). Normally, the processor should be run at its default VID (voltage identification) value as set during manufacturing. However, in the event the user needs to set a different VID value from the default value, it can be accomplished through a jumper block found on the board.

Note: These headers are not populated by default. EmVRD11 Controller VID input 0 and 7 are tied low. Initial boards will not have the VID Header populated, CPU1 must have VID override enabled for the initial Dual-Core Intel Xeon processor LV samples. The, VID

	Dual-Core Intel® Xeon® processor LV with Intel® E7520 Chipset and Intel® 6300ESB ICH
April 2007	User’s Manual
Order Number: 311274-009	35