Intel GENE-8310 manual Intel Celeron M Processor Subcompact Board With LVDS, Ethernet

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SubCompact Board

SubCompact Board	G E N E - 8 3 1 0

GENE-8310

Intel® Celeron® M Processor

Subcompact Board

With LVDS, Ethernet,

6 Channel Audio & Mini PCI

GENE-8310 Rev. A Manual 2nd Ed.

Jan. 2006

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Contents Intel Celeron M Processor Subcompact Board With LVDS, Ethernet GENE-83106 Channel Audio & Mini PCI SubCompact BoardCopyright Notice Acknowledgments Packing List Chapter 2 Quick Installation Guide ContentsChapter 1 General Information Chapter 4 Driver Installation Chapter 3 Award BIOS SetupAppendix A Programming The Watchdog Timer I/O Information Appendix BIRQ Mapping Chart I/O Address MapChapter General InformationChapter 1 General Information 1 1.1 Introduction Superb Performance and Controllable Power UsageMultiple Display Modes Chapter 1 General InformationWide Expansion Capability 48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast Ethernet 1.2 FeaturesAC-97 3D Surround 5.1 Channel Audio Supports Type II CompactFlash MemorySystem 1.3 SpecificationsDisplay 4 USB 2.0 Ports Does not Two 5 x 2 Pin Headers Supportsupport Wake-up function Chapter 2 Quick Installation Guide Quick Installation GuidePart No. 2007831011 Printed in Taiwan JAN 2.1 Safety Precautions The Height of Cooling System Depends on Customer Cooling Device 2.2 Location of Connectors and Jumpers Component SideCFD1 DIMM1 Solder SideComponent Side 2.3 Mechanical DrawingThe Height of Cooling System Depends on Customer Cooling Device 103.51133.93 3.23 8.89 0.00 72.39 0.58 114.300.58 0.002.4 List of Jumpers JumpersLabel Function2.5 List of Connectors ConnectorsCN17 Open 2.6 Setting JumpersClosed 2.7 Clear CMOS Selection JP1 2.10 USB2.0 Port 1 Connector CN12.8 LCD Voltage Selection JP2 2.9 COM2 RI/+5V Selection JP52.12 Primary IDE Hard Drive Connector CN3 2.11 USB2.0 Port 2 Connector CN2DIO Address is 801H 2.13 Digital IO Connector CN4Name 2.14 Front Panel CN5 2.15 Serial Port COM2 Connector CN62.16 Parallel Port Connector CN7 2.18 4P Power Connector CN9 2.17 Dual Channel LVDS Connector CN8PinSignal 2.20 DVI Connector CN11 2.19 TV-Out Connector CN102.21 Audio Input/Output Connector CN12 2.23 External 5VSB/PWRGD Connector CN14 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN132.24 IrDA Connector CN15 G E N E - 82.26 Mini-DIN PS/2 Connector CN17 2.25 Fan Connector CN162.27 Serial Port COM1 Connector CN18 2.29 External Battery VBAT2 2.28 CRT Display Connector CN192.30 Mini PCI Slot MPCI1 2.31 CompactFlash Disk Slot CFD1G E N E - 8 3 1 Chapter 3 Award BIOS Setup Award BIOS Setup3.1 System Test and Initialization System configuration verificationStandard CMOS Features Entering SetupAdvanced BIOS Features Advanced Chipset FeaturesPnP/PCI Configurations Power Management SetupLoad Fail-Safe Defaults Load Optimized DefaultsSave and Exit Setup Set Supervisor/User PasswordExit Without Saving Chapter 4 Driver Installation Driver InstallationFollow the sequence below to install the drivers Chapter4 Drivers Installation 4.1 InstallationStep 4 - Install Realtek AC97 codec Driver Appendix Programming the Watchdog TimerAppendix A Programming the Watchdog Timer A-1 A.1 Programming Configuring Sequence DescriptionAppendix A Programming the Watchdog Timer A-2 2 Modify the Data of the Registers 1 Enter the MB PnP Mode3 Exit the MB PnP Mode WatchDog Timer Configuration Registers Configure Control Index=02hAppendix A Programming the Watchdog Timer A-4 WatchDog Timer Configuration Register Index=72h, Default=00h WatchDog Timer Control Register Index=71h, Default=00hWatchDog Timer Time-out Value Register Index=73h, Default=00h Appendix A Programming the Watchdog Timer A-5A.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK CALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21h RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20hCALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEARMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP Appendix A Programming the Watchdog Timer A-10 END MainSetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h call SuperioSetReg pop cx pop ax ret SetLogicDevice endpAppendix B I/O Information B-1 I/O InformationB.2 1st MB Memory Address Map B.1 I/O Address MapAppendix B I/O Information B-2 B.4 DMA Channel Assignments B.3 IRQ Mapping ChartAppendix B I/O Informaion B-3