Intel GENE-8310 manual Packing List

Page 4

SubCompact Board	G E N E - 8 3 1 0

Packing List

Before you begin installing your card, please make sure that the following materials have been shipped:

•1 GENE-8310 CPU Card

•1 IDE Cable

•1 KB/Mouse Cable

•2 USB Cable

•1 Audio Cable

•1 COM Port Cable

•1 TV-out and S-terminal Cable

•1 DVI Cable

•1 Parallel Port Cable

•1 Jumper Cap

•1 Quick Installation Guide

•1 CD-ROM for manual (in PDF format) and drivers

If any of these items should be missing or damaged, please contact your distributor or sales representative immediately.

iii

Image 4

Contents GENE-8310 Intel Celeron M Processor Subcompact Board With LVDS, Ethernet6 Channel Audio & Mini PCI SubCompact BoardCopyright Notice Acknowledgments Packing List Chapter 2 Quick Installation Guide ContentsChapter 1 General Information Chapter 4 Driver Installation Chapter 3 Award BIOS SetupAppendix A Programming The Watchdog Timer Appendix B I/O InformationIRQ Mapping Chart I/O Address MapChapter General InformationChapter 1 General Information 1 Superb Performance and Controllable Power Usage 1.1 IntroductionMultiple Display Modes Chapter 1 General InformationWide Expansion Capability 1.2 Features 48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast EthernetAC-97 3D Surround 5.1 Channel Audio Supports Type II CompactFlash Memory1.3 Specifications SystemDisplay 4 USB 2.0 Ports Does not Two 5 x 2 Pin Headers Supportsupport Wake-up function Chapter 2 Quick Installation Guide Quick Installation GuidePart No. 2007831011 Printed in Taiwan JAN 2.1 Safety Precautions 2.2 Location of Connectors and Jumpers Component Side The Height of Cooling System Depends on Customer Cooling DeviceSolder Side CFD1 DIMM12.3 Mechanical Drawing Component SideThe Height of Cooling System Depends on Customer Cooling Device 103.513.23 8.89 0.00 72.39 0.58 114.30 133.930.58 0.00Jumpers 2.4 List of JumpersLabel FunctionConnectors 2.5 List of ConnectorsCN17 Open 2.6 Setting JumpersClosed 2.10 USB2.0 Port 1 Connector CN1 2.7 Clear CMOS Selection JP12.8 LCD Voltage Selection JP2 2.9 COM2 RI/+5V Selection JP52.11 USB2.0 Port 2 Connector CN2 2.12 Primary IDE Hard Drive Connector CN3DIO Address is 801H 2.13 Digital IO Connector CN4Name 2.15 Serial Port COM2 Connector CN6 2.14 Front Panel CN52.16 Parallel Port Connector CN7 2.18 4P Power Connector CN9 2.17 Dual Channel LVDS Connector CN8PinSignal 2.20 DVI Connector CN11 2.19 TV-Out Connector CN102.21 Audio Input/Output Connector CN12 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN13 2.23 External 5VSB/PWRGD Connector CN142.24 IrDA Connector CN15 G E N E - 82.26 Mini-DIN PS/2 Connector CN17 2.25 Fan Connector CN162.27 Serial Port COM1 Connector CN18 2.28 CRT Display Connector CN19 2.29 External Battery VBAT22.30 Mini PCI Slot MPCI1 2.31 CompactFlash Disk Slot CFD1SubCompact Board Award BIOS Setup Chapter 3 Award BIOS SetupSystem configuration verification 3.1 System Test and InitializationEntering Setup Standard CMOS FeaturesAdvanced BIOS Features Advanced Chipset FeaturesPower Management Setup PnP/PCI ConfigurationsLoad Fail-Safe Defaults Load Optimized DefaultsSave and Exit Setup Set Supervisor/User PasswordExit Without Saving Driver Installation Chapter 4 Driver InstallationFollow the sequence below to install the drivers 4.1 Installation Chapter4 Drivers InstallationStep 4 - Install Realtek AC97 codec Driver Appendix Programming the Watchdog TimerAppendix A Programming the Watchdog Timer A-1 A.1 Programming Configuring Sequence DescriptionAppendix A Programming the Watchdog Timer A-2 2 Modify the Data of the Registers 1 Enter the MB PnP Mode3 Exit the MB PnP Mode WatchDog Timer Configuration Registers Configure Control Index=02hAppendix A Programming the Watchdog Timer A-4 WatchDog Timer Control Register Index=71h, Default=00h WatchDog Timer Configuration Register Index=72h, Default=00hWatchDog Timer Time-out Value Register Index=73h, Default=00h Appendix A Programming the Watchdog Timer A-5A.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20h CALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21hCALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEARMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP END Main Appendix A Programming the Watchdog Timer A-10SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h call SuperioSetReg pop cx pop ax ret SetLogicDevice endpI/O Information Appendix B I/O Information B-1B.2 1st MB Memory Address Map B.1 I/O Address MapAppendix B I/O Information B-2 B.4 DMA Channel Assignments B.3 IRQ Mapping ChartAppendix B I/O Informaion B-3