Intel GENE-8310 manual SubCompact Board, G E N E - 8 3 1

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	SubCompact Board		G E N E - 8 3 1 0

7	SDCS#1	32	SDCS#3
8	Ground	33	Ground
9	Ground	34	SDIOR#
10	Ground	35	SDIOW#
11	Ground	36	+5 Volt.
12	Ground	37	IRQ15
13	+5V	38	+5V
14	Ground	39	CSEL#
15	Ground	40	N/C
16	Ground	41	IDERST#
17	Ground	42	SIORDY
18	SDA2	43	N/C
19	SDA1	44	+5V
20	SDA0	45	DASP#
21	SDD0	46	PDIAG#
22	SDD1	47	SDD8
23	SDD2	48	SDD9
24	N/C	49	SDD10
25	Ground	50	Ground

Chapter 2 Quick Installation Guide 2-21

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Contents SubCompact Board GENE-8310Intel Celeron M Processor Subcompact Board With LVDS, Ethernet 6 Channel Audio & Mini PCICopyright Notice Acknowledgments Packing List Chapter 1 General Information ContentsChapter 2 Quick Installation Guide Appendix A Programming The Watchdog Timer Chapter 3 Award BIOS SetupChapter 4 Driver Installation I/O Address Map Appendix BI/O Information IRQ Mapping ChartChapter 1 General Information 1 General InformationChapter Chapter 1 General Information Superb Performance and Controllable Power Usage1.1 Introduction Multiple Display ModesWide Expansion Capability Supports Type II CompactFlash Memory 1.2 Features48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast Ethernet AC-97 3D Surround 5.1 Channel AudioSystem 1.3 SpecificationsDisplay support Wake-up function Two 5 x 2 Pin Headers Support4 USB 2.0 Ports Does not Part No. 2007831011 Printed in Taiwan JAN Quick Installation GuideChapter 2 Quick Installation Guide 2.1 Safety Precautions The Height of Cooling System Depends on Customer Cooling Device 2.2 Location of Connectors and Jumpers Component SideCFD1 DIMM1 Solder Side103.51 2.3 Mechanical DrawingComponent Side The Height of Cooling System Depends on Customer Cooling Device0.00 3.23 8.89 0.00 72.39 0.58 114.30133.93 0.58Function Jumpers2.4 List of Jumpers Label2.5 List of Connectors ConnectorsCN17 Closed 2.6 Setting JumpersOpen 2.9 COM2 RI/+5V Selection JP5 2.10 USB2.0 Port 1 Connector CN12.7 Clear CMOS Selection JP1 2.8 LCD Voltage Selection JP22.12 Primary IDE Hard Drive Connector CN3 2.11 USB2.0 Port 2 Connector CN2Name 2.13 Digital IO Connector CN4DIO Address is 801H 2.14 Front Panel CN5 2.15 Serial Port COM2 Connector CN62.16 Parallel Port Connector CN7 PinSignal 2.17 Dual Channel LVDS Connector CN82.18 4P Power Connector CN9 2.21 Audio Input/Output Connector CN12 2.19 TV-Out Connector CN102.20 DVI Connector CN11 G E N E - 8 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN132.23 External 5VSB/PWRGD Connector CN14 2.24 IrDA Connector CN152.27 Serial Port COM1 Connector CN18 2.25 Fan Connector CN162.26 Mini-DIN PS/2 Connector CN17 2.31 CompactFlash Disk Slot CFD1 2.28 CRT Display Connector CN192.29 External Battery VBAT2 2.30 Mini PCI Slot MPCI1G E N E - 8 3 1 Chapter 3 Award BIOS Setup Award BIOS Setup3.1 System Test and Initialization System configuration verificationAdvanced Chipset Features Entering SetupStandard CMOS Features Advanced BIOS FeaturesLoad Optimized Defaults Power Management SetupPnP/PCI Configurations Load Fail-Safe DefaultsExit Without Saving Set Supervisor/User PasswordSave and Exit Setup Chapter 4 Driver Installation Driver InstallationFollow the sequence below to install the drivers Chapter4 Drivers Installation 4.1 InstallationStep 4 - Install Realtek AC97 codec Driver Appendix A Programming the Watchdog Timer A-1 Programming the Watchdog TimerAppendix Appendix A Programming the Watchdog Timer A-2 Configuring Sequence DescriptionA.1 Programming 3 Exit the MB PnP Mode 1 Enter the MB PnP Mode2 Modify the Data of the Registers Appendix A Programming the Watchdog Timer A-4 Configure Control Index=02hWatchDog Timer Configuration Registers Appendix A Programming the Watchdog Timer A-5 WatchDog Timer Control Register Index=71h, Default=00hWatchDog Timer Configuration Register Index=72h, Default=00h WatchDog Timer Time-out Value Register Index=73h, Default=00hA.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEAR RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20hCALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21h CALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STCMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP call SuperioSetReg pop cx pop ax ret SetLogicDevice endp END MainAppendix A Programming the Watchdog Timer A-10 SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07hAppendix B I/O Information B-1 I/O InformationAppendix B I/O Information B-2 B.1 I/O Address MapB.2 1st MB Memory Address Map Appendix B I/O Informaion B-3 B.3 IRQ Mapping ChartB.4 DMA Channel Assignments