Intel GENE-8310 manual Configure Control Index=02h, SubCompact Board, G E N E - 8 3 1

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SubCompact Board	G E N E - 8 3 1 0

WatchDog Timer Configuration Registers

Configure Control (Index=02h)

This register is write only. Its values are not sticky; that is to say, a hardware reset will automatically clear the bits, and does not require the software to clear them.

Appendix A Programming the Watchdog Timer A-4

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Contents GENE-8310 Intel Celeron M Processor Subcompact Board With LVDS, Ethernet6 Channel Audio & Mini PCI SubCompact BoardCopyright Notice Acknowledgments Packing List Contents Chapter 2 Quick Installation GuideChapter 1 General Information Chapter 3 Award BIOS Setup Chapter 4 Driver InstallationAppendix A Programming The Watchdog Timer Appendix B I/O InformationIRQ Mapping Chart I/O Address MapGeneral Information ChapterChapter 1 General Information 1 Superb Performance and Controllable Power Usage 1.1 IntroductionMultiple Display Modes Chapter 1 General InformationWide Expansion Capability 1.2 Features 48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast EthernetAC-97 3D Surround 5.1 Channel Audio Supports Type II CompactFlash Memory1.3 Specifications SystemDisplay Two 5 x 2 Pin Headers Support 4 USB 2.0 Ports Does notsupport Wake-up function Quick Installation Guide Chapter 2 Quick Installation GuidePart No. 2007831011 Printed in Taiwan JAN 2.1 Safety Precautions 2.2 Location of Connectors and Jumpers Component Side The Height of Cooling System Depends on Customer Cooling DeviceSolder Side CFD1 DIMM12.3 Mechanical Drawing Component SideThe Height of Cooling System Depends on Customer Cooling Device 103.513.23 8.89 0.00 72.39 0.58 114.30 133.930.58 0.00Jumpers 2.4 List of JumpersLabel FunctionConnectors 2.5 List of ConnectorsCN17 2.6 Setting Jumpers OpenClosed 2.10 USB2.0 Port 1 Connector CN1 2.7 Clear CMOS Selection JP12.8 LCD Voltage Selection JP2 2.9 COM2 RI/+5V Selection JP52.11 USB2.0 Port 2 Connector CN2 2.12 Primary IDE Hard Drive Connector CN32.13 Digital IO Connector CN4 DIO Address is 801HName 2.15 Serial Port COM2 Connector CN6 2.14 Front Panel CN52.16 Parallel Port Connector CN7 2.17 Dual Channel LVDS Connector CN8 2.18 4P Power Connector CN9PinSignal 2.19 TV-Out Connector CN10 2.20 DVI Connector CN112.21 Audio Input/Output Connector CN12 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN13 2.23 External 5VSB/PWRGD Connector CN142.24 IrDA Connector CN15 G E N E - 82.25 Fan Connector CN16 2.26 Mini-DIN PS/2 Connector CN172.27 Serial Port COM1 Connector CN18 2.28 CRT Display Connector CN19 2.29 External Battery VBAT22.30 Mini PCI Slot MPCI1 2.31 CompactFlash Disk Slot CFD1SubCompact Board Award BIOS Setup Chapter 3 Award BIOS SetupSystem configuration verification 3.1 System Test and InitializationEntering Setup Standard CMOS FeaturesAdvanced BIOS Features Advanced Chipset FeaturesPower Management Setup PnP/PCI ConfigurationsLoad Fail-Safe Defaults Load Optimized DefaultsSet Supervisor/User Password Save and Exit SetupExit Without Saving Driver Installation Chapter 4 Driver InstallationFollow the sequence below to install the drivers 4.1 Installation Chapter4 Drivers InstallationStep 4 - Install Realtek AC97 codec Driver Programming the Watchdog Timer AppendixAppendix A Programming the Watchdog Timer A-1 Configuring Sequence Description A.1 ProgrammingAppendix A Programming the Watchdog Timer A-2 1 Enter the MB PnP Mode 2 Modify the Data of the Registers3 Exit the MB PnP Mode Configure Control Index=02h WatchDog Timer Configuration RegistersAppendix A Programming the Watchdog Timer A-4 WatchDog Timer Control Register Index=71h, Default=00h WatchDog Timer Configuration Register Index=72h, Default=00hWatchDog Timer Time-out Value Register Index=73h, Default=00h Appendix A Programming the Watchdog Timer A-5A.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20h CALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21hCALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEARMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP END Main Appendix A Programming the Watchdog Timer A-10SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h call SuperioSetReg pop cx pop ax ret SetLogicDevice endpI/O Information Appendix B I/O Information B-1B.1 I/O Address Map B.2 1st MB Memory Address MapAppendix B I/O Information B-2 B.3 IRQ Mapping Chart B.4 DMA Channel AssignmentsAppendix B I/O Informaion B-3