Intel GENE-8310 manual A.1 Programming, Configuring Sequence Description

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SubCompact Board	G E N E - 8 3 1 0

A.1 Programming

GENE-8310 utilizes ITE 8712 chipset as its watchdog timer controller. Below are the procedures to complete its configuration and the AAEON intial watchdog timer program is also attached based on which you can develop customized program to fit your application.

Configuring Sequence Description

After the hardware reset or power-on reset, the ITE 8712 enters the normal mode with all logical devices disabled except KBC. The initial state (enable bit ) of this logical device (KBC) is determined by the state of pin 121 (DTR1#) at the falling edge of the system reset during power-on reset.

There are three steps to complete the configuration setup: (1) Enter the MB PnP Mode; (2) Modify the data of configuration registers; (3) Exit the MB PnP Mode. Undesired result may

Appendix A Programming the Watchdog Timer A-2

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Contents 6 Channel Audio & Mini PCI GENE-8310Intel Celeron M Processor Subcompact Board With LVDS, Ethernet SubCompact BoardCopyright Notice Acknowledgments Packing List Chapter 2 Quick Installation Guide ContentsChapter 1 General Information Chapter 4 Driver Installation Chapter 3 Award BIOS SetupAppendix A Programming The Watchdog Timer IRQ Mapping Chart Appendix BI/O Information I/O Address MapChapter General InformationChapter 1 General Information 1 Multiple Display Modes Superb Performance and Controllable Power Usage1.1 Introduction Chapter 1 General InformationWide Expansion Capability AC-97 3D Surround 5.1 Channel Audio 1.2 Features48-bit Dual Channels LVDS TFT LCD 10/100Mbps Fast Ethernet Supports Type II CompactFlash Memory1.3 Specifications SystemDisplay 4 USB 2.0 Ports Does not Two 5 x 2 Pin Headers Supportsupport Wake-up function Chapter 2 Quick Installation Guide Quick Installation GuidePart No. 2007831011 Printed in Taiwan JAN 2.1 Safety Precautions 2.2 Location of Connectors and Jumpers Component Side The Height of Cooling System Depends on Customer Cooling DeviceSolder Side CFD1 DIMM1The Height of Cooling System Depends on Customer Cooling Device 2.3 Mechanical DrawingComponent Side 103.510.58 3.23 8.89 0.00 72.39 0.58 114.30133.93 0.00Label Jumpers2.4 List of Jumpers FunctionConnectors 2.5 List of ConnectorsCN17 Open 2.6 Setting JumpersClosed 2.8 LCD Voltage Selection JP2 2.10 USB2.0 Port 1 Connector CN12.7 Clear CMOS Selection JP1 2.9 COM2 RI/+5V Selection JP52.11 USB2.0 Port 2 Connector CN2 2.12 Primary IDE Hard Drive Connector CN3DIO Address is 801H 2.13 Digital IO Connector CN4Name 2.15 Serial Port COM2 Connector CN6 2.14 Front Panel CN52.16 Parallel Port Connector CN7 2.18 4P Power Connector CN9 2.17 Dual Channel LVDS Connector CN8PinSignal 2.20 DVI Connector CN11 2.19 TV-Out Connector CN102.21 Audio Input/Output Connector CN12 2.24 IrDA Connector CN15 2.22 Ethernet 10/100Base-TX RJ-45 Phone Jack Connector CN132.23 External 5VSB/PWRGD Connector CN14 G E N E - 82.26 Mini-DIN PS/2 Connector CN17 2.25 Fan Connector CN162.27 Serial Port COM1 Connector CN18 2.30 Mini PCI Slot MPCI1 2.28 CRT Display Connector CN192.29 External Battery VBAT2 2.31 CompactFlash Disk Slot CFD1SubCompact Board Award BIOS Setup Chapter 3 Award BIOS SetupSystem configuration verification 3.1 System Test and InitializationAdvanced BIOS Features Entering SetupStandard CMOS Features Advanced Chipset FeaturesLoad Fail-Safe Defaults Power Management SetupPnP/PCI Configurations Load Optimized DefaultsSave and Exit Setup Set Supervisor/User PasswordExit Without Saving Driver Installation Chapter 4 Driver InstallationFollow the sequence below to install the drivers 4.1 Installation Chapter4 Drivers InstallationStep 4 - Install Realtek AC97 codec Driver Appendix Programming the Watchdog TimerAppendix A Programming the Watchdog Timer A-1 A.1 Programming Configuring Sequence DescriptionAppendix A Programming the Watchdog Timer A-2 2 Modify the Data of the Registers 1 Enter the MB PnP Mode3 Exit the MB PnP Mode WatchDog Timer Configuration Registers Configure Control Index=02hAppendix A Programming the Watchdog Timer A-4 WatchDog Timer Time-out Value Register Index=73h, Default=00h WatchDog Timer Control Register Index=71h, Default=00hWatchDog Timer Configuration Register Index=72h, Default=00h Appendix A Programming the Watchdog Timer A-5A.2 ITE8712 Watchdog Timer Initial Program game port enable mov cl call SetLogicDevice InitialOK CALL ReadConfigurationData CMP AL,12h JNE NotInitial NeedInitial STC RET ExitConfigurationMode ENDP CheckChip PROC NEAR MOV AL,20hCALL ReadConfigurationData CMP AL,87h JNE NotInitial MOV AL,21h RET NotInitial CLC RET CheckChip ENDP ReadConfigurationData PROC NEARMOV DX,WORD PTR CSCfgPort+06h IN AL,DX RET ReadConfigurationData ENDP SetLogicDevice proc near push ax push cx xchg al,cl mov cl,07h END MainAppendix A Programming the Watchdog Timer A-10 call SuperioSetReg pop cx pop ax ret SetLogicDevice endpI/O Information Appendix B I/O Information B-1B.2 1st MB Memory Address Map B.1 I/O Address MapAppendix B I/O Information B-2 B.4 DMA Channel Assignments B.3 IRQ Mapping ChartAppendix B I/O Informaion B-3