Intel IQ80332 manual Memory Subsystem, Battery Backup

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Intel® IQ80332 I/O Processor

Hardware Reference Section

3.4Memory Subsystem

The Memory Controller of 80332 controls the DDR SDRAM memory subsystem. It features pro- grammable chip selects and support for error correction codes (ECC). The memory controller can be configured for DDR SDRAM at 333 MHz and DDR-II at 400 MHz. The memory controller supports pipelined access and arbitration control to maximize performance. The memory controller interface configuration support includes Unbuffered DIMMs, Registered DIMMs, and discrete

DDR SDRAM devices.

This IQ80332 has DDR-II at 400 MHz DIMM on the board. The memory subsystem of the evaluation board consists of the SDRAM as well as the Flash memory subsystems.

3.4.1DDR SDRAM

The DDR SDRAM interface consists of a 64-bit wide data path to support up to 3.2 Gbytes/sec throughput. An 8-bit Error Correction Code (ECC) is stored into the DDRII SDRAM array along with the data and is checked when the data is read.

The IQ80332 features on board registered DDRII 400 MHz SDRAM, arranged 512 Mbit x16 in density (256 MB), and with ECC.

3.4.1.1Battery Backup

Battery backup is provided to save any information in DDR during a power failure. The evaluation board contains a 4V Li-ion battery, a charging circuit and a regulator circuit.

DDRII technology provides enabling data preservation through the self-refresh command. When the processor receives an active Primary PCI-X reset, the self-refresh command issues, driving SCKE signals low. Upon seeing this condition, the board logic circuit holds SCKE low before the processor loses power. Batteries maintain power to DDRII and logic, to ensure self-refresh mode. When the circuit detects PRST# returning to inactive state, the circuit releases the hold on SCKE. Removing the battery can disable the battery circuit. When the battery remains in the platform when it is de-powered and/or removed from the chassis, the battery maintains DDRII for about four hours. Once power is reapplied, the battery is fully charged.

The CPLD contains information in regards to the battery status. Please see Section 3.6.7, “Battery Status” on page 34 for more details.

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Contents Intel IQ80332 I/O Processor Evaluation Platform Board ManualIntel IQ80332 I/O Processor Evaluation Platform Board Manual Contents 6.3 2.2 Figures Examples Date Revision Description Revision History001 Initial Release Document Purpose and Scope Other Related DocumentsElectronic Information Component ReferencesElectronic Information Component ReferenceTerms and Definitions Terms and DefinitionsDefinition Intel 80332 I/O Processor 231 Summary of Features Feature DefinitionHardware Installation Kit ContentFirst-Time Installation and Test Power Requirements Factory Settings Contents of the FlashDevelopment Strategy Supported Tool BucketsRedHat RedBoot Target MonitorsSerial-UART Communication Host Communications ExamplesJtag Debug Communication Network Communication Network Communication ExampleCommunicating with RedBoot GNUPro GDB/InsightIntel IQ80332 I/O Processor Connecting with GDB GDB set remotebaudThis Page Left Intentionally Blank Functional Diagram Target MarketForm-Factor/Connectivity Features Board Form-Factor/ConnectivityPower Power FeaturesBattery Backup Memory SubsystemFlash Memory Requirements Flash Memory RequirementsExternal Interrupt Routing to Intel 80332 I/O Processor Interrupt RoutingInterrupt System Resource Peripheral Bus Features 80332 populates the peripheral bus as depicted by FigureFlash ROM Features Flash ROMRotary Switch UartNon-Volatile RAM Audio BuzzerBattery Status Buffer Requirements Battery StatusRead Name Description Write Debug Interface Console Serial PortJtag Port Jtag DebugJtag Port Pin-out Board Reset Scheme Reset Requirements/SchemesSwitches and Jumpers Switch SummaryDefault Switch Settings of S7A1- Visual Switch SummaryJumper Summary Connector SummaryGeneral Purpose Input/Output Header Detail Descriptions of Switches/Jumpers Switch S1C2 80332 ResetSwitch S6A1 BPCI-X Reset Switch S8A1 RotarySwitch S7A1-3 Retry Settings and Operation Mode S7A1-4 PCI-X Bus B Speed Enable Settings and Operation ModeS7A1-9 Operation Mode S7A1-8 Operation ModeS7A1-10 Operation Mode Jumper J1C1 Jtag Chain Jumper J7D1 Flash bit-widthJumper J1D2 Uart Control Jumper J9D3 Buzzer Volume Control Jumper J7B4 SMBus HeaderDram Components on the Peripheral BusSoftware Reference Peripheral Bus Memory Map Address Range in Hex Size Data Bus Width DescriptionBoard Support Package BSP Examples Intel 80332 I/O Processor Memory MapRedBoot Intel 80332 I/O Processor Files RedBoot* Intel 80332 I/O Processor Memory MapVirtual Address Physical Address Size Description RedBoot 80332 DDR Memory Initialization Sequence IQ80321 and IQ80332 Comparisons This Page Left Intentionally Blank Introduction PurposeRelated Web Sites Setup Hardware SetupSoftware Setup Software Flow DiagramNew Project Setup Creating a New ProjectConfiguration Flashing with Jtag OverviewUsing Flash Programmer Debugging Out of Flash Building an Executable File From Example CodeRunning the CodeLab Debugger Launching and Configuring DebuggerManually Loading and Executing an Application Program Using Breakpoints Displaying Source CodeSetting CodeLab Debug Options Stepping Through the CodeExploring the CodeLab Debug Windows Watch Window Registers WindowVariables Window Debugging Basics Hardware and Software BreakpointsSoftware Breakpoints Hardware Breakpoints3 C.9.3 Exceptions/Trapping

IQ80332 specifications

The Intel IQ80332 is a high-performance microprocessor designed primarily for embedded applications, showcasing Intel's commitment to delivering powerful computing solutions for a variety of industries. Launched as part of Intel’s post-Pentium architecture, the IQ80332 is built on a robust architecture that combines efficiency with advanced performance capabilities, making it particularly suitable for industrial, telecommunications, and networking environments.

One of the standout features of the IQ80332 is its support for wireless communication technologies, providing seamless connectivity options for embedded devices. The chip integrates advanced power management features, enabling it to operate efficiently, which is crucial for systems that demand low power consumption without sacrificing performance.

The processor is built on a scalable architecture that supports a wide range of applications, from simple control operations to complex data processing tasks. It has a diverse instruction set, allowing developers to leverage a variety of programming paradigms for optimizing application performance. This versatility makes the IQ80332 a preferred choice for developers looking to build sophisticated embedded systems.

Another key characteristic of the IQ80332 processor is its robust security features. It includes hardware-level security measures that help protect sensitive data and maintain system integrity—an essential requirement in today’s connected environments where cyber threats are prevalent.

Additionally, the Intel IQ80332 supports multiple system interfaces, allowing for easy integration with various peripherals. Its compatibility with industry-standard buses makes it an ideal choice for upgrading existing systems without extensive redesign efforts.

Moreover, the chip is capable of running multiple operating systems, which provides developers with flexibility in choosing the best software platforms for their applications. This multitasking ability contributes to its efficiency, making it a noteworthy contender in the embedded processing market.

In summary, the Intel IQ80332 microprocessor is characterized by high performance, low power consumption, and robust security features. Its versatility, combined with advanced connectivity options and strong support for multiple operating systems, makes it a valuable asset in the development of next-generation embedded systems across a multitude of sectors. As industries continue to evolve, the IQ80332 remains a compelling solution for engineers and developers seeking reliable and efficient computing power.
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