
Chapter 1: Introduction
1.3DATA FLOW IN THE HSIM-W87
The T3 port receives the DS3 data through the coaxial interface. A T3 framer/Multiplexer strips off the T3 framing and provides 28 individual T1 data streams. The T1 data streams are then terminated by T1 framers, which provide an HDLC bit stream to the HDLC controller. The controller receives data packets from each of the bit streams and places them in a memory subsystem. An onboard CPU examines the packet and notifies the host of its arrival. Finally, a Cabletron proprietary ASIC transfers the data to the host platform.
This process is followed in reverse when a packet is transmitted from the host platform out the T3 port. The host platform notifies the
1.4FEATURES
•Data Transfer Rates of 45 Mbps in full duplex, when running all 28 T1s carrying continuous data traffic of
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•T1 Inverse Multiplexing (IMUX)
•WAN IP Priority Queuing functionality
•DS1 Alarm Thresholds
•SNMP support
•DS1 and DS3 MIB Support
•LANVIEW LEDs
1.4.1Connectivity
The
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