Quatech RS-422/485, MPA-200/300 user manual Baud Rate Generator Programming

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3.2Baud Rate Generator Programming

The baud rate generator (hereafter referred to as the BRG) of the SCC consists of a 16-bit down counter, two 8-bit time constant registers, and an output divide-by- two. The time constant for the BRG is programmed into WR12 (least significant byte) and WR13 (most significant byte). The equation relating the baud rate to the time constant is given below while Table 4 shows the time constants associated with a number of popular baud rates when using the standard MPA-200 9.8304 MHz clock.

Clock_Frequency

Time_Const ￿ 2￿Baud_Rate￿Clock_Mode ￿ 2

Where:

Clock_Frequency = crystal frequency of 9.8304 MHz

Clock_Mode = value programmed in WR4

Baud_Rate = desired baud rate

Table 4 Time constants for common baud rates

Baud Rate

Baud Constant (Hex)

38400 - - - - - - - - - - - - - - - - - - - - - - - 007EH 19200 - - - - - - - - - - - - - - - - - - - - - - - 00FEH 9600 - - - - - - - - - - - - - - - - - - - - - - - - 01FEH 4800 - - - - - - - - - - - - - - - - - - - - - - - - 03FEH 2400 - - - - - - - - - - - - - - - - - - - - - - - - 07FEH 1200 - - - - - - - - - - - - - - - - - - - - - - - - 0FFEH 600 - - - - - - - - - - - - - - - - - - - - - - - - - 1FFEH 300 - - - - - - - - - - - - - - - - - - - - - - - - - 3FFEH

(for 9.8304 Mhz Clock)

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Quatech Inc., MPA-200/300 Manual

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Contents QUATECH, INC MPA-200/300Page Warranty Information Page Compliances Electromagnetic Emissions Table of Contents Quatech Inc., MPA-200/300 Manual Introduction MPA-200 board drawing IRQ DMA/DRQ Hardware InstallationSCC General Information Accessing the registers RR3 RR0RR1 RR2WR3 WR0WR1 WR2Baud Rate Generator Programming SCC Data Encoding Methods IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Jumper Block ConfigurationsJ4 Interrupt Configuration J5 & J6 Interrupt Level SelectionJ10 Transmit DMA Channel Selection IRQ10 IRQ11 IRQ12 IRQ14 IRQ15J7 Line Driver Control Selection J11 Receive DMA Channel SelectionSynca Rlen OUT J8 Synca to Rlen controlBase Address = 3F8H AddressingPage Interrupts Direct Memory Access Page Reqa Configuration Register D0 -TXSRC, Transmit DMA Source D1 -RXSRC, Receive DMA SourceTM ST Llen Rlen Rcken Tcken Rxden Txden Communications RegisterD0 -TRANSMITTER Enable D1 -RECEIVER EnableDTE / DCE Configuration Rrclk Rtclk Trxca Tclk Ttclk DTE ConfigurationDCE Configuration DCE Clock Configuration External Connections CTS Ctsa +DSR Dcda DTR DTR/REQA DSR Dcda +RRCLK Trxc Test ModeTest Mode Null-Modem Cables Connector Notation +RXD,-RXD Circuit AB Signal Ground Connector Notation DgndCircuit CC Data SET Ready DSR Connector Notation +DSR,-DSR Connector Notation +TXD,-TXDCircuit CB Clear to Send CTS Connector Notation +CTS,-CTS Connector Notation +RTCLK,-RTCLKConnector Notation +RRCLK,-RRCLK Circuit CA Request to Send RTS Connector Notation +RTS,-RTSCircuit CD DTE Ready DTR Connector Notation +DTR,-DTR Circuit LL Local Loopback LL Connector Notation LlbkCircuit RL Remote Loopback RL Connector Notation Rlbk Circuit TM Test Mode TM Connector Notation Test Mode Specifications MPA-200/300 Version March