Quatech RS-422/485, MPA-200/300 Communications Register, TM ST Llen Rlen Rcken Tcken Rxden Txden

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9 COMMUNICATIONS REGISTER

The MPA-200 is equipped with an onboard communications register which gives the user options pertaining to the clocks and testing. The user can specify the source and type of clock to be transmitted or received. Test mode bits pertain only to the DTE versions and can be ignored if using a MPA-200 configured DCE.

The address of this register is Base+4. Table 14 and the descriptions that follow detail the communications register.

NOTE:

The Local Loopback Test and the Remote Loopback Test cannot be performed simultaneously. Thus, bits D5 and D4 of the communications register should not be simultaneously set (logic 1) .

Table 14 COMMUNICATIONS Register - Read/Write

D7

D6

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

TM ST

0

LLEN

RLEN

RCKEN

TCKEN

RXDEN

TXDEN

D7 -TEST MODE STATUS (DTE only, read only):

This bit can read the status of the Test Mode signal on a DTE, allowing the user to monitor this signal without generating any interrupts.

D6 - Reserved, always 0.

D5 -LOCAL LOOPBACK ENABLE (DTE only):

When set (logic 1), this bit allows the DTE to test the functioning of the DTE/DCE interface and the transmit and receive sections of the local DCE. When cleared (logic 0), no testing occurs.

D4 -REMOTE LOOPBACK ENABLE (DTE only):

When set (logic 1), this bit allows the DTE to test the transmission path up to and through the remote DCE to the DTE interface and the similar return transmission path. When cleared (logic 0), no testing occurs. If jumper J8 is in place the Remote Loopback is also used to control the Sync input of the Channel A data receiver. This is useful in situations where it is desired to receive unformatted serial data.

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Quatech Inc., MPA-200/300 Manual

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Contents QUATECH, INC MPA-200/300Page Warranty Information Page Compliances Electromagnetic Emissions Table of Contents Quatech Inc., MPA-200/300 Manual Introduction MPA-200 board drawing IRQ DMA/DRQ Hardware InstallationSCC General Information Accessing the registers RR1 RR0RR2 RR3WR1 WR0WR2 WR3Baud Rate Generator Programming SCC Data Encoding Methods J4 Interrupt Configuration Jumper Block ConfigurationsJ5 & J6 Interrupt Level Selection IRQ3 IRQ4 IRQ5 IRQ6 IRQ7J10 Transmit DMA Channel Selection IRQ10 IRQ11 IRQ12 IRQ14 IRQ15J7 Line Driver Control Selection J11 Receive DMA Channel SelectionSynca Rlen OUT J8 Synca to Rlen controlBase Address = 3F8H AddressingPage Interrupts Direct Memory Access Page Reqa Configuration Register D0 -TXSRC, Transmit DMA Source D1 -RXSRC, Receive DMA SourceTM ST Llen Rlen Rcken Tcken Rxden Txden Communications RegisterD0 -TRANSMITTER Enable D1 -RECEIVER EnableDTE / DCE Configuration Rrclk Rtclk Trxca Tclk Ttclk DTE ConfigurationDCE Configuration DCE Clock Configuration External Connections CTS Ctsa +DSR Dcda DTR DTR/REQA DSR Dcda +RRCLK Trxc Test ModeTest Mode Null-Modem Cables Circuit CC Data SET Ready DSR Connector Notation +DSR,-DSR Circuit AB Signal Ground Connector Notation DgndConnector Notation +TXD,-TXD Connector Notation +RXD,-RXDConnector Notation +RRCLK,-RRCLK Connector Notation +RTCLK,-RTCLKCircuit CA Request to Send RTS Connector Notation +RTS,-RTS Circuit CB Clear to Send CTS Connector Notation +CTS,-CTSCircuit RL Remote Loopback RL Connector Notation Rlbk Circuit CD DTE Ready DTR Connector Notation +DTR,-DTRCircuit LL Local Loopback LL Connector Notation Llbk Circuit TM Test Mode TM Connector Notation Test Mode Specifications MPA-200/300 Version March