Quatech MPA-200/300, RS-422/485 user manual DTE Configuration, Rrclk Rtclk Trxca Tclk Ttclk

Page 32

10.1 DTE Configuration

The control signals that the DTE can generate are the Request To Send (RTS) and Data Terminal Ready (DTR). It can receive the signals Carrier Detect (CD), Clear to Send (CTS), and Data Set Ready (DSR). All of the control signals are controlled through channel A of the SCC, with the exception of the DSR signal, which is received on channel B.

The DTE’s transmit clock (TCLK from the SCC TRXCA pin) can be transmitted on TTCLK or received on RTCLK depending on TCKEN (D2 of the communica- tions register). The receive clock (RCLK from the SCC RTxC pins) can be received on RRCLK or can be generated on the TRxCB pin of the SCC, depend- ing on RCKEN ( D3 of the communications register). The DTE can not transmit its RCLK. Figure 4 illustrates the clock circuitry of the MPA-200 for it's DTE configuration.

Figure 2 DTE Clock Configuration

RTXCA

(RCLK)

RTXCB

TRXCB

RCKEN

TCKEN

RRCLK

RTCLK

TRXCA (TCLK)

TTCLK

The testing signals that the DTE can generate are the Local Loopback Test (LL) and the Remote Loopback Test (RL). These signals are can be controlled through the onboard communications register. The DTE can generate an interrupt when a Test Mode (TM) condition is received. Table 15 summarizes the signals on the DTE.

Quatech Inc., MPA-200/300 Manual

26

Image 32
Contents MPA-200/300 QUATECH, INCPage Warranty Information Page Compliances Electromagnetic Emissions Table of Contents Quatech Inc., MPA-200/300 Manual Introduction MPA-200 board drawing Hardware Installation IRQ DMA/DRQSCC General Information Accessing the registers RR0 RR1RR2 RR3WR0 WR1WR2 WR3Baud Rate Generator Programming SCC Data Encoding Methods Jumper Block Configurations J4 Interrupt ConfigurationJ5 & J6 Interrupt Level Selection IRQ3 IRQ4 IRQ5 IRQ6 IRQ7IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 J10 Transmit DMA Channel SelectionJ11 Receive DMA Channel Selection J7 Line Driver Control SelectionJ8 Synca to Rlen control Synca Rlen OUTAddressing Base Address = 3F8HPage Interrupts Direct Memory Access Page Reqa Configuration Register D1 -RXSRC, Receive DMA Source D0 -TXSRC, Transmit DMA Source Communications Register TM ST Llen Rlen Rcken Tcken Rxden TxdenD1 -RECEIVER Enable D0 -TRANSMITTER EnableDTE / DCE Configuration DTE Configuration Rrclk Rtclk Trxca Tclk TtclkDCE Configuration DCE Clock Configuration External Connections DTR DTR/REQA DSR Dcda +RRCLK Trxc Test Mode CTS Ctsa +DSR DcdaTest Mode Null-Modem Cables Circuit AB Signal Ground Connector Notation Dgnd Circuit CC Data SET Ready DSR Connector Notation +DSR,-DSRConnector Notation +TXD,-TXD Connector Notation +RXD,-RXDConnector Notation +RTCLK,-RTCLK Connector Notation +RRCLK,-RRCLKCircuit CA Request to Send RTS Connector Notation +RTS,-RTS Circuit CB Clear to Send CTS Connector Notation +CTS,-CTSCircuit RL Remote Loopback RL Connector Notation Rlbk Circuit CD DTE Ready DTR Connector Notation +DTR,-DTRCircuit LL Local Loopback LL Connector Notation Llbk Circuit TM Test Mode TM Connector Notation Test Mode Specifications MPA-200/300 Version March